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hw/misc, hw/ssi: Fix some URLs for AMD / Xilinx models

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It seems that the url changed a bit, and it triggers an error.  Fix the URLs so
the documentation can be reached again.

Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20231124143505.1493184-3-fkonrad@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Frederic Konrad 2023-11-24 14:35:04 +00:00 committed by Peter Maydell
parent 90bb6d6764
commit a9bc470ec2
5 changed files with 5 additions and 5 deletions
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2
hw/dma/xlnx_csu_dma.c
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@ -33,7 +33,7 @@
/*
* Ref: UG1087 (v1.7) February 8, 2019
* https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
* https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers
* CSUDMA Module section
*/
REG32(ADDR, 0x0)

2
include/hw/misc/xlnx-versal-cframe-reg.h
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@ -12,7 +12,7 @@
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
*
* [2] Versal ACAP Register Reference,
* https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
* https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFRAME_REG-Module
*/
#ifndef HW_MISC_XLNX_VERSAL_CFRAME_REG_H
#define HW_MISC_XLNX_VERSAL_CFRAME_REG_H

2
include/hw/misc/xlnx-versal-cfu.h
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@ -12,7 +12,7 @@
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
*
* [2] Versal ACAP Register Reference,
* https://www.xilinx.com/htmldocs/registers/am012/am012-versal-register-reference.html
* https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU_CSR-Module
*/
#ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H
#define HW_MISC_XLNX_VERSAL_CFU_APB_H

2
include/hw/misc/xlnx-versal-pmc-iou-slcr.h
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@ -34,7 +34,7 @@
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
*
* [2] Versal ACAP Register Reference,
* https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html
* https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module
*
* QEMU interface:
* + sysbus MMIO region 0: MemoryRegion for the device's registers

2
include/hw/ssi/xlnx-versal-ospi.h
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@ -34,7 +34,7 @@
* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
*
* [2] Versal ACAP Register Reference,
* https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___ospi.html
* https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSPI-Module
*
*
* QEMU interface: