target/microblaze: Cleanup mb_cpu_do_interrupt
Reindent; remove dead/commented code. Use D_FLAG to set ESS[DS]. Sink MSR adjustment for kernel entry, iflags and res_addr clear. Improve CPU_LOG_INT formatting; report pc and msr before and after. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
64603d1eff
commit
a9f614587b
@ -111,6 +111,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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uint32_t t, msr = mb_cpu_read_msr(env);
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bool set_esr;
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/* IMM flag cannot propagate across a branch and into the dslot. */
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assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG));
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@ -118,142 +119,114 @@ void mb_cpu_do_interrupt(CPUState *cs)
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assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG);
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/* RTI flags are private to translate. */
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assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
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env->res_addr = RES_ADDR_NONE;
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switch (cs->exception_index) {
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case EXCP_HW_EXCP:
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if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
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qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
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return;
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}
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case EXCP_HW_EXCP:
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if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Exception raised on system without exceptions!\n");
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return;
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}
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env->regs[17] = env->pc + 4;
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env->esr &= ~(1 << 12);
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qemu_log_mask(CPU_LOG_INT,
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"INT: HWE at pc=%08x msr=%08x iflags=%x\n",
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env->pc, msr, env->iflags);
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/* Exception breaks branch + dslot sequence? */
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if (env->iflags & D_FLAG) {
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env->esr |= 1 << 12 ;
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env->btr = env->btarget;
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}
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/* Exception breaks branch + dslot sequence? */
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set_esr = true;
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env->esr &= ~D_FLAG;
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if (env->iflags & D_FLAG) {
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env->esr |= D_FLAG;
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env->btr = env->btarget;
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}
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/* Disable the MMU. */
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t = (msr & (MSR_VM | MSR_UM)) << 1;
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msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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msr |= t;
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/* Exception in progress. */
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msr |= MSR_EIP;
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mb_cpu_write_msr(env, msr);
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/* Exception in progress. */
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msr |= MSR_EIP;
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env->regs[17] = env->pc + 4;
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env->pc = cpu->cfg.base_vectors + 0x20;
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break;
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qemu_log_mask(CPU_LOG_INT,
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"hw exception at pc=%x ear=%" PRIx64 " "
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"esr=%x iflags=%x\n",
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env->pc, env->ear,
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env->esr, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->iflags = 0;
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env->pc = cpu->cfg.base_vectors + 0x20;
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break;
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case EXCP_MMU:
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qemu_log_mask(CPU_LOG_INT,
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"INT: MMU at pc=%08x msr=%08x "
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"ear=%" PRIx64 " iflags=%x\n",
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env->pc, msr, env->ear, env->iflags);
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case EXCP_MMU:
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/* Exception breaks branch + dslot sequence? */
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set_esr = true;
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env->esr &= ~D_FLAG;
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if (env->iflags & D_FLAG) {
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env->esr |= D_FLAG;
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env->btr = env->btarget;
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/* Reexecute the branch. */
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env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4);
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} else if (env->iflags & IMM_FLAG) {
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/* Reexecute the imm. */
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env->regs[17] = env->pc - 4;
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} else {
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env->regs[17] = env->pc;
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}
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qemu_log_mask(CPU_LOG_INT,
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"MMU exception at pc=%x iflags=%x ear=%" PRIx64 "\n",
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env->pc, env->iflags, env->ear);
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/* Exception in progress. */
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msr |= MSR_EIP;
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env->pc = cpu->cfg.base_vectors + 0x20;
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break;
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env->esr &= ~(1 << 12);
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/* Exception breaks branch + dslot sequence? */
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if (env->iflags & D_FLAG) {
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env->esr |= 1 << 12 ;
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env->btr = env->btarget;
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case EXCP_IRQ:
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assert(!(msr & (MSR_EIP | MSR_BIP)));
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assert(msr & MSR_IE);
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assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
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/* Reexecute the branch. */
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env->regs[17] -= 4;
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/* was the branch immprefixed?. */
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if (env->iflags & BIMM_FLAG) {
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env->regs[17] -= 4;
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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}
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} else if (env->iflags & IMM_FLAG) {
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env->regs[17] -= 4;
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}
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qemu_log_mask(CPU_LOG_INT,
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"INT: DEV at pc=%08x msr=%08x iflags=%x\n",
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env->pc, msr, env->iflags);
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set_esr = false;
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/* Disable the MMU. */
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t = (msr & (MSR_VM | MSR_UM)) << 1;
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msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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msr |= t;
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/* Exception in progress. */
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msr |= MSR_EIP;
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mb_cpu_write_msr(env, msr);
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/* Disable interrupts. */
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msr &= ~MSR_IE;
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env->regs[14] = env->pc;
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env->pc = cpu->cfg.base_vectors + 0x10;
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break;
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qemu_log_mask(CPU_LOG_INT,
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"exception at pc=%x ear=%" PRIx64 " iflags=%x\n",
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env->pc, env->ear, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->iflags = 0;
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env->pc = cpu->cfg.base_vectors + 0x20;
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break;
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case EXCP_HW_BREAK:
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assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
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case EXCP_IRQ:
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assert(!(msr & (MSR_EIP | MSR_BIP)));
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assert(msr & MSR_IE);
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assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
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qemu_log_mask(CPU_LOG_INT,
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"INT: BRK at pc=%08x msr=%08x iflags=%x\n",
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env->pc, msr, env->iflags);
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set_esr = false;
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t = (msr & (MSR_VM | MSR_UM)) << 1;
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/* Break in progress. */
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msr |= MSR_BIP;
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env->regs[16] = env->pc;
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env->pc = cpu->cfg.base_vectors + 0x18;
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break;
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#if 0
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#include "disas/disas.h"
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default:
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cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index);
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/* not reached */
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}
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/* Useful instrumentation when debugging interrupt issues in either
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the models or in sw. */
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{
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const char *sym;
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/* Save previous mode, disable mmu, disable user-mode. */
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t = (msr & (MSR_VM | MSR_UM)) << 1;
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msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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msr |= t;
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mb_cpu_write_msr(env, msr);
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sym = lookup_symbol(env->pc);
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if (sym
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&& (!strcmp("netif_rx", sym)
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|| !strcmp("process_backlog", sym))) {
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env->res_addr = RES_ADDR_NONE;
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env->iflags = 0;
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qemu_log("interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
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env->pc, msr, t, env->iflags, sym);
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log_cpu_state(cs, 0);
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}
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}
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#endif
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qemu_log_mask(CPU_LOG_INT,
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"interrupt at pc=%x msr=%x %x iflags=%x\n",
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env->pc, msr, t, env->iflags);
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msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE);
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msr |= t;
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mb_cpu_write_msr(env, msr);
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env->regs[14] = env->pc;
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env->iflags = 0;
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env->pc = cpu->cfg.base_vectors + 0x10;
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//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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break;
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case EXCP_HW_BREAK:
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assert(!(env->iflags & (D_FLAG | IMM_FLAG)));
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t = (msr & (MSR_VM | MSR_UM)) << 1;
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qemu_log_mask(CPU_LOG_INT,
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"break at pc=%x msr=%x %x iflags=%x\n",
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env->pc, msr, t, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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msr |= t;
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msr |= MSR_BIP;
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env->regs[16] = env->pc;
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env->iflags = 0;
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env->pc = cpu->cfg.base_vectors + 0x18;
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mb_cpu_write_msr(env, msr);
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break;
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default:
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cpu_abort(cs, "unhandled exception type=%d\n",
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cs->exception_index);
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break;
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if (!set_esr) {
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qemu_log_mask(CPU_LOG_INT,
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" to pc=%08x msr=%08x\n", env->pc, msr);
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} else if (env->esr & D_FLAG) {
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qemu_log_mask(CPU_LOG_INT,
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" to pc=%08x msr=%08x esr=%04x btr=%08x\n",
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env->pc, msr, env->esr, env->btr);
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} else {
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qemu_log_mask(CPU_LOG_INT,
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" to pc=%08x msr=%08x esr=%04x\n",
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env->pc, msr, env->esr);
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}
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}
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