target-ppc: Introduce TEXASRU Bit Fields
Define mnemonics for the various bit fields in the Transaction EXception And Summary Register (TEXASR). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -558,6 +558,26 @@ struct ppc_slb_t {
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#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
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#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
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/* Transaction EXception And Summary Register bits */
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#define TEXASR_FAILURE_PERSISTENT (63 - 7)
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#define TEXASR_DISALLOWED (63 - 8)
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#define TEXASR_NESTING_OVERFLOW (63 - 9)
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#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
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#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
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#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
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#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
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#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
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#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
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#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
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#define TEXASR_ABORT (63 - 31)
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#define TEXASR_SUSPENDED (63 - 32)
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#define TEXASR_PRIVILEGE_HV (63 - 34)
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#define TEXASR_PRIVILEGE_PR (63 - 35)
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#define TEXASR_FAILURE_SUMMARY (63 - 36)
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#define TEXASR_TFIAR_EXACT (63 - 37)
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#define TEXASR_ROT (63 - 38)
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#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
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enum {
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POWERPC_FLAG_NONE = 0x00000000,
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/* Flag for MSR bit 25 signification (VRE/SPE) */
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