OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

pcie: simplify range check

Browse Source 
Simplify code slighly by reversing the polarity
for the range check

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
This commit is contained in:
Michael S. Tsirkin 2010-10-25 07:03:24 +02:00
parent 5afb986917
commit ac0cdda347
1 changed files with 61 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
hw/pcie.c
View File

@ -19,6 +19,7 @@
*/
#include "sysemu.h"
#include "range.h"
#include "pci_bridge.h"
#include "pcie.h"
#include "msix.h"
@ -296,6 +297,10 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
return;
}
PCIE_DEV_PRINTF(dev,
"addr: 0x%"PRIx32" val: 0x%"PRIx32" len: %d\n"
"\tsltctl_prev: 0x%02"PRIx16" sltctl: 0x%02"PRIx16
@ -303,9 +308,9 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
addr, val, len, sltctl_prev, sltctl, sltsta);
/* SLTCTL */
if (ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
PCIE_DEV_PRINTF(dev, "sltctl: 0x%02"PRIx16" -> 0x%02"PRIx16"\n",
sltctl_prev, sltctl);
if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
PCI_EXP_SLTCTL_EIC)) {
sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
@ -344,19 +349,24 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
sltctl_prev, sltctl);
}
/* command completion.
* Real hardware might take a while to complete
* requested command because physical movement would be involved
* like locking the electromechanical lock.
* However in our case, command is completed instantaneously above,
* so send a command completion event right now.
*
/*
* 6.7.3.2 Command Completed Events
*
* Software issues a command to a hot-plug capable Downstream Port by
* issuing a write transaction that targets any portion of the Port’s Slot
* Control register. A single write to the Slot Control register is
* considered to be a single command, even if the write affects more than
* one field in the Slot Control register. In response to this transaction,
* the Port must carry out the requested actions and then set the
* associated status field for the command completed event. */
/* Real hardware might take a while to complete requested command because
* physical movement would be involved like locking the electromechanical
* lock. However in our case, command is completed instantaneously above,
* so send a command completion event right now.
*/
/* set command completed bit */
pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
}
}
void pcie_cap_slot_push_attention_button(PCIDevice *dev)
{