target/arm: Reorg NEON VLD/VST all elements
Instead of shifts and masks, use direct loads and stores from the neon register file. Mirror the iteration structure of the ARM pseudocode more closely. Correct the parameters of the VLD2 A2 insn. Note that this includes a bugfix for handling of the insn "VLD2 (multiple 2-element structures)" -- we were using an incorrect stride value. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181011205206.3552-19-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7377c2c97e
commit
ac55d00709
@ -1611,12 +1611,56 @@ static TCGv_i32 neon_load_reg(int reg, int pass)
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return tmp;
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}
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static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)
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{
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long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
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switch (mop) {
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case MO_UB:
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tcg_gen_ld8u_i64(var, cpu_env, offset);
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break;
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case MO_UW:
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tcg_gen_ld16u_i64(var, cpu_env, offset);
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break;
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case MO_UL:
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tcg_gen_ld32u_i64(var, cpu_env, offset);
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break;
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case MO_Q:
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tcg_gen_ld_i64(var, cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void neon_store_reg(int reg, int pass, TCGv_i32 var)
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{
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tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
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tcg_temp_free_i32(var);
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}
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static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)
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{
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long offset = neon_element_offset(reg, ele, size);
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switch (size) {
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case MO_8:
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tcg_gen_st8_i64(var, cpu_env, offset);
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break;
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case MO_16:
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tcg_gen_st16_i64(var, cpu_env, offset);
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break;
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case MO_32:
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tcg_gen_st32_i64(var, cpu_env, offset);
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break;
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case MO_64:
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tcg_gen_st_i64(var, cpu_env, offset);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static inline void neon_load_reg64(TCGv_i64 var, int reg)
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{
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tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
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@ -4885,16 +4929,16 @@ static struct {
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int interleave;
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int spacing;
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} const neon_ls_element_type[11] = {
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{4, 4, 1},
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{4, 4, 2},
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{1, 4, 1},
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{1, 4, 2},
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{4, 1, 1},
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{4, 2, 1},
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{3, 3, 1},
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{3, 3, 2},
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{2, 2, 2},
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{1, 3, 1},
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{1, 3, 2},
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{3, 1, 1},
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{1, 1, 1},
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{2, 2, 1},
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{2, 2, 2},
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{1, 2, 1},
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{1, 2, 2},
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{2, 1, 1}
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};
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@ -4915,6 +4959,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
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int shift;
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int n;
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int vec_size;
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int mmu_idx;
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TCGMemOp endian;
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TCGv_i32 addr;
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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@ -4936,6 +4982,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
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rn = (insn >> 16) & 0xf;
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rm = insn & 0xf;
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load = (insn & (1 << 21)) != 0;
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endian = s->be_data;
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mmu_idx = get_mem_index(s);
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if ((insn & (1 << 23)) == 0) {
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/* Load store all elements. */
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op = (insn >> 8) & 0xf;
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@ -4960,104 +5008,34 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
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nregs = neon_ls_element_type[op].nregs;
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interleave = neon_ls_element_type[op].interleave;
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spacing = neon_ls_element_type[op].spacing;
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if (size == 3 && (interleave | spacing) != 1)
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if (size == 3 && (interleave | spacing) != 1) {
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return 1;
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}
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tmp64 = tcg_temp_new_i64();
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addr = tcg_temp_new_i32();
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tmp2 = tcg_const_i32(1 << size);
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load_reg_var(s, addr, rn);
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stride = (1 << size) * interleave;
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for (reg = 0; reg < nregs; reg++) {
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if (interleave > 2 || (interleave == 2 && nregs == 2)) {
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load_reg_var(s, addr, rn);
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tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
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} else if (interleave == 2 && nregs == 4 && reg == 2) {
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load_reg_var(s, addr, rn);
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tcg_gen_addi_i32(addr, addr, 1 << size);
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}
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if (size == 3) {
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tmp64 = tcg_temp_new_i64();
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if (load) {
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gen_aa32_ld64(s, tmp64, addr, get_mem_index(s));
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neon_store_reg64(tmp64, rd);
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} else {
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neon_load_reg64(tmp64, rd);
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gen_aa32_st64(s, tmp64, addr, get_mem_index(s));
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}
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tcg_temp_free_i64(tmp64);
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tcg_gen_addi_i32(addr, addr, stride);
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} else {
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for (pass = 0; pass < 2; pass++) {
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if (size == 2) {
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if (load) {
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tmp = tcg_temp_new_i32();
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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neon_store_reg(rd, pass, tmp);
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} else {
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tmp = neon_load_reg(rd, pass);
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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tcg_temp_free_i32(tmp);
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}
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tcg_gen_addi_i32(addr, addr, stride);
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} else if (size == 1) {
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if (load) {
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tmp = tcg_temp_new_i32();
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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tcg_gen_addi_i32(addr, addr, stride);
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tmp2 = tcg_temp_new_i32();
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gen_aa32_ld16u(s, tmp2, addr, get_mem_index(s));
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tcg_gen_addi_i32(addr, addr, stride);
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tcg_gen_shli_i32(tmp2, tmp2, 16);
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tcg_gen_or_i32(tmp, tmp, tmp2);
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tcg_temp_free_i32(tmp2);
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neon_store_reg(rd, pass, tmp);
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} else {
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tmp = neon_load_reg(rd, pass);
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tmp2 = tcg_temp_new_i32();
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tcg_gen_shri_i32(tmp2, tmp, 16);
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
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tcg_temp_free_i32(tmp);
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tcg_gen_addi_i32(addr, addr, stride);
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gen_aa32_st16(s, tmp2, addr, get_mem_index(s));
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tcg_temp_free_i32(tmp2);
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tcg_gen_addi_i32(addr, addr, stride);
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}
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} else /* size == 0 */ {
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if (load) {
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tmp2 = NULL;
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for (n = 0; n < 4; n++) {
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tmp = tcg_temp_new_i32();
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gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
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tcg_gen_addi_i32(addr, addr, stride);
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if (n == 0) {
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tmp2 = tmp;
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} else {
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tcg_gen_shli_i32(tmp, tmp, n * 8);
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tcg_gen_or_i32(tmp2, tmp2, tmp);
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tcg_temp_free_i32(tmp);
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}
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}
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neon_store_reg(rd, pass, tmp2);
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} else {
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tmp2 = neon_load_reg(rd, pass);
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for (n = 0; n < 4; n++) {
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tmp = tcg_temp_new_i32();
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if (n == 0) {
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tcg_gen_mov_i32(tmp, tmp2);
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} else {
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tcg_gen_shri_i32(tmp, tmp2, n * 8);
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}
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gen_aa32_st8(s, tmp, addr, get_mem_index(s));
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tcg_temp_free_i32(tmp);
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tcg_gen_addi_i32(addr, addr, stride);
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}
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tcg_temp_free_i32(tmp2);
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}
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for (n = 0; n < 8 >> size; n++) {
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int xs;
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for (xs = 0; xs < interleave; xs++) {
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int tt = rd + reg + spacing * xs;
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if (load) {
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gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
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neon_store_element64(tt, n, size, tmp64);
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} else {
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neon_load_element64(tmp64, tt, n, size);
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gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
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}
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tcg_gen_add_i32(addr, addr, tmp2);
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}
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}
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rd += spacing;
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}
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tcg_temp_free_i32(addr);
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stride = nregs * 8;
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tcg_temp_free_i32(tmp2);
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tcg_temp_free_i64(tmp64);
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stride = nregs * interleave * 8;
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} else {
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size = (insn >> 10) & 3;
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if (size == 3) {
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