From 44d827ea69e6d0e1d7f1855b155ebe02a2b7768a Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 01/20] qtest/meson.build: check CONFIG_TCG for prom-env-test in qtests_ppc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 'prom-env-test' is a TCG test that will fail if QEMU is compiled with --disable-tcg: $ QTEST_QEMU_BINARY=./qemu-system-ppc64 ./tests/qtest/prom-env-test /ppc64/prom-env/mac99: qemu-system-ppc64: -accel tcg: invalid accelerator tcg (... hangs indefinitely ...) Fix it by checking CONFIG_TCG before compiling prom-env-test. Cc: Thomas Huth Signed-off-by: Daniel Henrique Barboza Reviewed-by: Thomas Huth Message-Id: <20220303153517.168943-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/qtest/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 7d8c74fdba..7b74d3116a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -160,7 +160,8 @@ qtests_ppc = \ (slirp.found() ? ['test-netfilter'] : []) + \ (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ (config_all_devices.has_key('CONFIG_M48T59') ? ['m48t59-test'] : []) + \ - ['boot-order-test', 'prom-env-test', 'boot-serial-test'] \ + (config_all_devices.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + \ + ['boot-order-test', 'boot-serial-test'] qtests_ppc64 = \ qtests_ppc + \ From 74884cb1a6d0fa193a20b2d1bb1131f50eb2732a Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 02/20] qtest/meson.build: check CONFIG_TCG for boot-serial-test in qtests_ppc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 'boot-serial-test' does not work with a QEMU built with --disable-tcg in a IBM POWER9 host. The reason is that without TCG QEMU will default to KVM acceleration, but then the KVM module in IBM POWER hosts aren't able to handle other CPUs. The result is that the test will break with a KVM error when trying to ruin the ppce500 test: $ QTEST_QEMU_BINARY=./qemu-system-ppc64 ./tests/qtest/boot-serial-test /ppc64/boot-serial/ppce500: qemu-system-ppc64: -accel tcg: invalid accelerator tcg error: kvm run failed Invalid argument NIP 0000000000f00000 LR 0000000000000000 CTR 0000000000000000 XER 0000000000000000 CPU#0 MSR 0000000000000000 HID0 0000000000000000 HF 24020002 iidx 1 didx 1 TB 00000000 00000000 DECR 0 (...) ** (./tests/qtest/boot-serial-test:1935760): ERROR **: 07:44:03.010: Failed to find expected string. Please check '/tmp/qtest-boot-serial-sJ78sqg' Fix it by checking CONFIG_TCG before compiling boot-serial-test. Cc: Thomas Huth Signed-off-by: Daniel Henrique Barboza Reviewed-by: Thomas Huth Message-Id: <20220303153517.168943-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/qtest/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 7b74d3116a..d25f82bb5a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -161,7 +161,8 @@ qtests_ppc = \ (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ (config_all_devices.has_key('CONFIG_M48T59') ? ['m48t59-test'] : []) + \ (config_all_devices.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + \ - ['boot-order-test', 'boot-serial-test'] + (config_all_devices.has_key('CONFIG_TCG') ? ['boot-serial-test'] : []) + \ + ['boot-order-test'] qtests_ppc64 = \ qtests_ppc + \ From 6b87d614fed76a9256cda46f4b2d11b423493b57 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 03/20] avocado/boot_linux_console.py: check for tcg in test_ppc_powernv8/9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PowerNV8/9 machines does not work with KVM acceleration, meaning that boot_linux_console.py:BootLinuxConsole.test_ppc_powernv8/9 tests will always fail when QEMU is compiled with --disable-tcg: ERROR 1-tests/avocado/boot_linux_console.py:BootLinuxConsole.test_ppc_powernv8 -> VMLaunchFailure: ConnectError: Failed to establish session: [Errno 104] Connection reset by peer Exit code: 1 Command: ./qemu-system-ppc64 -display none -vga none -chardev socket,id=mon,path=/var/tmp/avo_qemu_sock_no19zg0m/qemu-1936936-7fffa77cff98-monitor.sock -mon chardev=mon,mode=control -machine powernv8 -chardev socket,id=console,path=/var/tmp/avo_qemu_sock_no19zg0m/qemu-1936936-7fffa77cff98-console.sock,server=on,wait=off -serial chardev:console -kernel /home/danielhb/avocado/data/cache/by_location/4514304e2c4ee84c5f0b5c8bacedda783891df68/zImage.epapr -append console=tty0 console=hvc0 -device pcie-pci-bridge,id=bridge1,bus=pcie.1,addr=0x0 -device nvme,bus=pcie.2,addr=0x0,serial=1234 -device e1000e,bus=bridge1,addr=0x3 -device nec-usb-xhci,bus=bridge1,addr=0x2 Output: qemu-system-ppc64: The powernv machine does not work with KVM acceleration Let's add the TCG accel requirement in both tests to skip them if we don't have TCG support available. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220303153517.168943-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/boot_linux_console.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index 9c618d4809..d7d9130329 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -1170,6 +1170,7 @@ class BootLinuxConsole(LinuxKernelTest): self.do_test_advcal_2018('19', tar_hash, 'uImage') def do_test_ppc64_powernv(self, proc): + self.require_accelerator("tcg") images_url = ('https://github.com/open-power/op-build/releases/download/v2.7/') kernel_url = images_url + 'zImage.epapr' @@ -1194,6 +1195,7 @@ class BootLinuxConsole(LinuxKernelTest): """ :avocado: tags=arch:ppc64 :avocado: tags=machine:powernv8 + :avocado: tags=accel:tcg """ self.do_test_ppc64_powernv('P8') @@ -1201,6 +1203,7 @@ class BootLinuxConsole(LinuxKernelTest): """ :avocado: tags=arch:ppc64 :avocado: tags=machine:powernv9 + :avocado: tags=accel:tcg """ self.do_test_ppc64_powernv('P9') From d78fb13d6b501f183e280f0b1bfb79480c478e84 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 04/20] avocado/boot_linux_console.py: check tcg accel in test_ppc64_e500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some ppc64 hosts (e.g. IBM POWER hosts) aren't able to run the e500 machine using KVM accel. Skip this test if TCG accel isn't available. Cc: Cleber Rosa Signed-off-by: Daniel Henrique Barboza Reviewed-by: Cédric Le Goater Message-Id: <20220303153517.168943-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/boot_linux_console.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index d7d9130329..6d6e748572 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -1165,7 +1165,9 @@ class BootLinuxConsole(LinuxKernelTest): :avocado: tags=arch:ppc64 :avocado: tags=machine:ppce500 :avocado: tags=cpu:e5500 + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") tar_hash = '6951d86d644b302898da2fd701739c9406527fe1' self.do_test_advcal_2018('19', tar_hash, 'uImage') From 89b65e3072d422a32897dfbe649d0df1013df80d Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 05/20] avocado/replay_kernel.py: make tcg-icount check in run_vm() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The icount framework relies on TCG availability. If QEMU is built with --disable-tcg we won't have icount either, and then this test will fail with the following message in an IBM POWER9 host: tests/avocado/replay_kernel.py:ReplayKernelNormal.test_ppc64_pseries: ERROR: ConnectError: Failed to establish session: (...) /11-tests_avocado_replay_kernel.py_ReplayKernelNormal.test_ppc64_pseries/replay.bin: cannot configure icount, TCG support not available Although this was revealed in a specific ppc64 scenario, the TCG check is being done in the common code inside run_vm() because all archs need TCG to have access to icount. Cc: Pavel Dovgalyuk Signed-off-by: Daniel Henrique Barboza Reviewed-by: Cédric Le Goater Message-Id: <20220303153517.168943-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/replay_kernel.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py index c68a953730..0b2b0dc692 100644 --- a/tests/avocado/replay_kernel.py +++ b/tests/avocado/replay_kernel.py @@ -36,6 +36,9 @@ class ReplayKernelBase(LinuxKernelTest): def run_vm(self, kernel_path, kernel_command_line, console_pattern, record, shift, args, replay_path): + # icount requires TCG to be available + self.require_accelerator('tcg') + logger = logging.getLogger('replay') start_time = time.time() vm = self.get_vm() @@ -243,6 +246,7 @@ class ReplayKernelNormal(ReplayKernelBase): """ :avocado: tags=arch:ppc64 :avocado: tags=machine:pseries + :avocado: tags=accel:tcg """ kernel_url = ('https://archives.fedoraproject.org/pub/archive' '/fedora-secondary/releases/29/Everything/ppc64le/os' From daff68ccd1780dfccd890b5849bbb176f0a51ef3 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 06/20] avocado/boot_linux_console.py: check TCG accel in test_ppc_g3beige() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This test breaks when run in an IBM POWER host with a QEMU compiled with --disable-tcg and the ppc-softmmu target. One thing to note is that the error message explictly mentions kvm_pr support: Command: ./qemu-system-ppc -display none -vga none (...) -machine g3beige (...) Output: ioctl(KVM_CREATE_VM) failed: 22 Invalid argument PPC KVM module is not loaded. Try modprobe kvm_pr. qemu-system-ppc: failed to initialize kvm: Invalid argument The host was running kvm_hv, not kvm_pr, and the machine failed to load. Unfortunately we don't have a way to detect whether the KVM module loaded is kvm_hv or kvm_pr - we do a check for /dev/kvm to detect KVM support but both modules create this file so that's not helpful. Let's skip this test for now until we have a way of detecting kvm_pr support in the host. Reported-by: Murilo Opsfelder Araujo Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/boot_linux_console.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index 6d6e748572..2f8d8e2fe6 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -1213,7 +1213,13 @@ class BootLinuxConsole(LinuxKernelTest): """ :avocado: tags=arch:ppc :avocado: tags=machine:g3beige + :avocado: tags=accel:tcg """ + # TODO: g3beige works with kvm_pr but we don't have a + # reliable way ATM (e.g. looking at /proc/modules) to detect + # whether we're running kvm_hv or kvm_pr. For now let's + # disable this test if we don't have TCG support. + self.require_accelerator("tcg") tar_hash = 'e0b872a5eb8fdc5bed19bd43ffe863900ebcedfc' self.vm.add_args('-M', 'graphics=off') self.do_test_advcal_2018('15', tar_hash, 'invaders.elf') From ff110c18bf22b746b8a30c295a64f8f1045d0397 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 07/20] avocado/boot_linux_console.py: check TCG accel in test_ppc_mac99() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This test breaks when run in an IBM POWER host with a QEMU compiled with --disable-tcg and the ppc-softmmu target in a similar manner as test_ppc_g3beige did. There's also an observation made about kvm_pr in the error message: Command: ./qemu-system-ppc -display none -vga none (...) -machine mac99 (...) Output: ioctl(KVM_CREATE_VM) failed: 22 Invalid argument PPC KVM module is not loaded. Try modprobe kvm_pr. qemu-system-ppc: failed to initialize kvm: Invalid argument This means that, when/if we're able to detect kvm_pr support in these avocado tests, we can revisit this test to not rely solely on TCG availability. Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/boot_linux_console.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index 2f8d8e2fe6..b40a3abc81 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -1228,7 +1228,13 @@ class BootLinuxConsole(LinuxKernelTest): """ :avocado: tags=arch:ppc :avocado: tags=machine:mac99 + :avocado: tags=accel:tcg """ + # TODO: mac99 works with kvm_pr but we don't have a + # reliable way ATM (e.g. looking at /proc/modules) to detect + # whether we're running kvm_hv or kvm_pr. For now let's + # disable this test if we don't have TCG support. + self.require_accelerator("tcg") tar_hash = 'e0b872a5eb8fdc5bed19bd43ffe863900ebcedfc' self.vm.add_args('-M', 'graphics=off') self.do_test_advcal_2018('15', tar_hash, 'invaders.elf') From d08b9b76580662e1064ece0b07b1c438fb6f571d Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 08/20] avocado/ppc_405.py: remove test_ppc_taihu() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Running this test gives us a deprecation warning telling that this machine type is no longer supported: Output: qemu-system-ppc: Machine type 'taihu' is deprecated: incomplete, use 'ref405ep' instead Moreover, this test fails to pass running in an IBM POWER host when building QEMU with --disable-tcg. Since the machine type is already being considered deprecated let's not bother fixing the test with --disable-tcg. Remove test_ppc_taihu(). Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_405.py | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tests/avocado/ppc_405.py b/tests/avocado/ppc_405.py index a47f89b934..a69b7c5e97 100644 --- a/tests/avocado/ppc_405.py +++ b/tests/avocado/ppc_405.py @@ -25,14 +25,6 @@ class Ppc405Machine(QemuSystemTest): wait_for_console_pattern(self, 'AMCC PPC405EP Evaluation Board') exec_command_and_wait_for_pattern(self, 'reset', 'AMCC PowerPC 405EP') - def test_ppc_taihu(self): - """ - :avocado: tags=arch:ppc - :avocado: tags=machine:taihu - :avocado: tags=cpu:405ep - """ - self.do_test_ppc405() - def test_ppc_ref405ep(self): """ :avocado: tags=arch:ppc From 6e73b98a1b2876a565414c4db03149217190b3cd Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 09/20] avocado/ppc_405.py: check TCG accel in test_ppc_ref405ep() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Running this test without TCG support in an IBM POWER server results in the following error: Command: ./qemu-system-ppc -display none -vga none (...) -machine ref405ep (...) Output: qemu-system-ppc: Register sync failed... If you're using kvm-hv.ko, only "-cpu host" is possible qemu-system-ppc: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument Although the host is running kvm_hv we don't have a way of differentiate between kvm_hv and kvm_pr, meaning that this test would've failed in the same way if kvm_pr was the KVM module loaded in the host. Since we don't have a way of checking which KVM module is being loaded when using avocado, make a TCG accel check in test_ppc_ref405ep(). Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_405.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/avocado/ppc_405.py b/tests/avocado/ppc_405.py index a69b7c5e97..4e7e01aa76 100644 --- a/tests/avocado/ppc_405.py +++ b/tests/avocado/ppc_405.py @@ -30,5 +30,7 @@ class Ppc405Machine(QemuSystemTest): :avocado: tags=arch:ppc :avocado: tags=machine:ref405ep :avocado: tags=cpu:405ep + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") self.do_test_ppc405() From 4e653f0aa8db4fb8f4fc48f0d5231f2b9bc3a9e5 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 10/20] avocado/ppc_74xx.py: check TCG accel for all tests MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All tests of this file, when running in an IBM POWER host and with --disable-tcg, fail in a similar manner: Command: ./qemu-system-ppc -display none -vga none (...) -cpu 7400 (...) Output: ioctl(KVM_CREATE_VM) failed: 22 Invalid argument PPC KVM module is not loaded. Try modprobe kvm_pr. qemu-system-ppc: failed to initialize kvm: Invalid argument We don't have a way of telling which KVM module is loaded in a Power host (kvm_hv or kvm_pr). For now let's make all the tests of this file depend on TCG support. Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_74xx.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tests/avocado/ppc_74xx.py b/tests/avocado/ppc_74xx.py index 556a9a7da9..f54757c243 100644 --- a/tests/avocado/ppc_74xx.py +++ b/tests/avocado/ppc_74xx.py @@ -11,6 +11,7 @@ from avocado_qemu import wait_for_console_pattern class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=arch:ppc + :avocado: tags=accel:tcg """ timeout = 5 @@ -18,6 +19,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7400 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -27,6 +29,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7410 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -36,6 +39,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7441 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -45,6 +49,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7445 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -54,6 +59,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7447 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -63,6 +69,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7447a """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -72,6 +79,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7448 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -81,6 +89,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7450 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -90,6 +99,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7451 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -99,6 +109,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7455 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -108,6 +119,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7457 """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') @@ -117,6 +129,7 @@ class ppc74xxCpu(QemuSystemTest): """ :avocado: tags=cpu:7457a """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, '>> OpenBIOS') From 52b7fb79ed8e406c86d4b9e98b9047df2d7fadfc Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 11/20] avocado/ppc_bamboo.py: check TCG accel in test_ppc_bamboo() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This tests times out in an IBM POWER host when compiled with --disable-tcg. Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_bamboo.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/avocado/ppc_bamboo.py b/tests/avocado/ppc_bamboo.py index 40629e3478..102ff252df 100644 --- a/tests/avocado/ppc_bamboo.py +++ b/tests/avocado/ppc_bamboo.py @@ -20,7 +20,9 @@ class BambooMachine(QemuSystemTest): :avocado: tags=machine:bamboo :avocado: tags=cpu:440epb :avocado: tags=device:rtl8139 + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") tar_url = ('http://landley.net/aboriginal/downloads/binaries/' 'system-image-powerpc-440fp.tar.gz') tar_hash = '53e5f16414b195b82d2c70272f81c2eedb39bad9' From 32768847b7c902a84f8d291797206b575e105d94 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 12/20] avocado/ppc_mpc8544ds.py: check TCG accel in test_ppc_mpc8544ds() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This tests times out in an IBM POWER host when compiled with --disable-tcg. Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_mpc8544ds.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/avocado/ppc_mpc8544ds.py b/tests/avocado/ppc_mpc8544ds.py index 886f967b15..8d6a749201 100644 --- a/tests/avocado/ppc_mpc8544ds.py +++ b/tests/avocado/ppc_mpc8544ds.py @@ -19,7 +19,9 @@ class Mpc8544dsMachine(QemuSystemTest): """ :avocado: tags=arch:ppc :avocado: tags=machine:mpc8544ds + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") tar_url = ('https://www.qemu-advent-calendar.org' '/2020/download/day17.tar.gz') tar_hash = '7a5239542a7c4257aa4d3b7f6ddf08fb6775c494' From 486ff2896e5bab24403545068dafc1e21bb5c38c Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 13/20] avocado/ppc_prep_40p.py: check TCG accel in all tests MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All tests in the file times out when running in an IBM POWER host and --disable-tcg with an error like the following: Command: ./qemu-system-ppc -display none -vga none (...) -machine 40p (...) Output: qemu-system-ppc: Register sync failed... If you're using kvm-hv.ko, only "-cpu host" is possible qemu-system-ppc: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument Since we don't have a way to detect whether the host is running kvm_hv or kvm_pr, skip all tests if TCG is not available. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220310183011.110391-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_prep_40p.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/avocado/ppc_prep_40p.py b/tests/avocado/ppc_prep_40p.py index 4bd956584d..d4f1eb7e1d 100644 --- a/tests/avocado/ppc_prep_40p.py +++ b/tests/avocado/ppc_prep_40p.py @@ -28,7 +28,9 @@ class IbmPrep40pMachine(QemuSystemTest): :avocado: tags=machine:40p :avocado: tags=os:netbsd :avocado: tags=slowness:high + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") bios_url = ('http://ftpmirror.your.org/pub/misc/' 'ftp.software.ibm.com/rs6000/firmware/' '7020-40p/P12H0456.IMG') @@ -51,7 +53,9 @@ class IbmPrep40pMachine(QemuSystemTest): """ :avocado: tags=arch:ppc :avocado: tags=machine:40p + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") self.vm.set_console() self.vm.add_args('-m', '192') # test fw_cfg @@ -65,7 +69,9 @@ class IbmPrep40pMachine(QemuSystemTest): :avocado: tags=arch:ppc :avocado: tags=machine:40p :avocado: tags=os:netbsd + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") drive_url = ('https://archive.netbsd.org/pub/NetBSD-archive/' 'NetBSD-7.1.2/iso/NetBSD-7.1.2-prep.iso') drive_hash = 'ac6fa2707d888b36d6fa64de6e7fe48e' From b719411673386187862218892f21b3974987f9c3 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 14/20] avocado/ppc_virtex_ml507.py: check TCG accel in test_ppc_virtex_ml507() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This test times out when running in an IBM POWER host and --disable-tcg. Signed-off-by: Daniel Henrique Barboza Message-Id: <20220310183011.110391-10-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/avocado/ppc_virtex_ml507.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/avocado/ppc_virtex_ml507.py b/tests/avocado/ppc_virtex_ml507.py index a6912ee579..6b07686b56 100644 --- a/tests/avocado/ppc_virtex_ml507.py +++ b/tests/avocado/ppc_virtex_ml507.py @@ -19,7 +19,9 @@ class VirtexMl507Machine(QemuSystemTest): """ :avocado: tags=arch:ppc :avocado: tags=machine:virtex-ml507 + :avocado: tags=accel:tcg """ + self.require_accelerator("tcg") tar_url = ('https://www.qemu-advent-calendar.org' '/2020/download/hippo.tar.gz') tar_hash = '306b95bfe7d147f125aa176a877e266db8ef914a' From c6242335b3ff504a552ceba18c8b8ab9dc684a77 Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 15/20] target/ppc: fix ISI fault cause for Radix MMU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix Instruction Storage Interrupt (ISI) fault cause for Radix MMU, when caused by missing PAGE_EXEC permission, to be SRR1_NOEXEC_GUARD instead of DSISR_PROTFAULT. This matches POWER9 hardware behavior. Fixes: d5fee0bbe68 ("target/ppc: Implement ISA V3.00 radix page fault handler") Signed-off-by: Leandro Lupori Message-Id: <20220309192756.145283-1-leandro.lupori@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/mmu-radix64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 67c38f065b..5414fd63c1 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -204,7 +204,8 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type, /* Check if requested access type is allowed */ need_prot = prot_for_access_type(access_type); if (need_prot & ~*prot) { /* Page Protected for that Access */ - *fault_cause |= DSISR_PROTFAULT; + *fault_cause |= access_type == MMU_INST_FETCH ? SRR1_NOEXEC_GUARD : + DSISR_PROTFAULT; return true; } From 52d324ff13fcf97bc31f2e24803e366d330aa7cc Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 16/20] target/ppc: fix xxspltw for big endian hosts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix a typo in the host endianness macro and add a simple test to detect regressions. Fixes: 9bb0048ec6f8 ("target/ppc: convert xxspltw to vector operations") Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson Message-Id: <20220310172047.61094-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/translate/vsx-impl.c.inc | 2 +- tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/xxspltw.c | 46 +++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/ppc64le/xxspltw.c diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 48a97b2d7e..e67fbf2bb8 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1552,7 +1552,7 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim2 *a) tofs = vsr_full_offset(a->xt); bofs = vsr_full_offset(a->xb); bofs += a->uim << MO_32; -#ifndef HOST_WORDS_BIG_ENDIAN +#ifndef HOST_WORDS_BIGENDIAN bofs ^= 8 | 4; #endif diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index c9498053df..8197c288a7 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -27,5 +27,6 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10 run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10 PPC64_TESTS += signal_save_restore_xer +PPC64_TESTS += xxspltw TESTS += $(PPC64_TESTS) diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target index 12d85e946b..9624bb1e9c 100644 --- a/tests/tcg/ppc64le/Makefile.target +++ b/tests/tcg/ppc64le/Makefile.target @@ -25,5 +25,6 @@ run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10 PPC64LE_TESTS += mtfsf PPC64LE_TESTS += signal_save_restore_xer +PPC64LE_TESTS += xxspltw TESTS += $(PPC64LE_TESTS) diff --git a/tests/tcg/ppc64le/xxspltw.c b/tests/tcg/ppc64le/xxspltw.c new file mode 100644 index 0000000000..4cff78bfdc --- /dev/null +++ b/tests/tcg/ppc64le/xxspltw.c @@ -0,0 +1,46 @@ +#include +#include +#include +#include + +#define WORD_A 0xAAAAAAAAUL +#define WORD_B 0xBBBBBBBBUL +#define WORD_C 0xCCCCCCCCUL +#define WORD_D 0xDDDDDDDDUL + +#define DWORD_HI (WORD_A << 32 | WORD_B) +#define DWORD_LO (WORD_C << 32 | WORD_D) + +#define TEST(HI, LO, UIM, RES) \ + do { \ + union { \ + uint64_t u; \ + double f; \ + } h = { .u = HI }, l = { .u = LO }; \ + /* \ + * Use a pair of FPRs to load the VSR avoiding insns \ + * newer than xxswapd. \ + */ \ + asm("xxmrghd 32, %0, %1\n\t" \ + "xxspltw 32, 32, %2\n\t" \ + "xxmrghd %0, 32, %0\n\t" \ + "xxswapd 32, 32\n\t" \ + "xxmrghd %1, 32, %1\n\t" \ + : "+f" (h.f), "+f" (l.f) \ + : "i" (UIM) \ + : "v0"); \ + printf("xxspltw(0x%016" PRIx64 "%016" PRIx64 ", %d) =" \ + " %016" PRIx64 "%016" PRIx64 "\n", HI, LO, UIM, \ + h.u, l.u); \ + assert(h.u == (RES)); \ + assert(l.u == (RES)); \ + } while (0) + +int main(void) +{ + TEST(DWORD_HI, DWORD_LO, 0, WORD_A << 32 | WORD_A); + TEST(DWORD_HI, DWORD_LO, 1, WORD_B << 32 | WORD_B); + TEST(DWORD_HI, DWORD_LO, 2, WORD_C << 32 | WORD_C); + TEST(DWORD_HI, DWORD_LO, 3, WORD_D << 32 | WORD_D); + return 0; +} From 5d927bceaf882770790800d8069fcaa0c9034a7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 17/20] ppc/xive2: Make type Xive2EndSource not user creatable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xive2EndSource objects can only be instantiated through a Xive2Router (PnvXive2). Reported-by: Thomas Huth Fixes: f8a233dedf25 ("ppc/xive2: Introduce a XIVE2 core framework") Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater --- hw/intc/xive2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index b6452f1478..3aff42a69e 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1000,6 +1000,7 @@ static void xive2_end_source_class_init(ObjectClass *klass, void *data) dc->desc = "XIVE END Source"; device_class_set_props(dc, xive2_end_source_properties); dc->realize = xive2_end_source_realize; + dc->user_creatable = false; } static const TypeInfo xive2_end_source_info = { From d3df1f64704d0a189270703ff6406fcfebfd1913 Mon Sep 17 00:00:00 2001 From: Frederic Barrat Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 18/20] ppc/pnv: Introduce a pnv-phb5 device to match root port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We already have the pnv-phb3 and pnv-phb4 devices for POWER8 and POWER9 respectively. POWER10 uses version 5 of the PHB. It is very close to the PHB4 from POWER9, at least in our model and we could almost keep using the PHB4 model. However the matching root port pnv-phb5-root-port is specific to POWER10 so to avoid confusion as well as making it easy to introduce differences later, we create a pnv-phb5 class, which is mostly an alias for pnv-phb4 for now. With this patch, the command line for a user-created PHB on powernv10 becomes: -machine powernv10 -nodefaults -device pnv-phb5 -device pnv-phb5-root-port Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater Message-Id: <20220310155101.294568-2-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 7 +++++++ hw/pci-host/pnv_phb4_pec.c | 9 +++++---- include/hw/pci-host/pnv_phb4.h | 5 +++++ 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b5b384e9ee..d1a911f988 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1783,6 +1783,12 @@ static const TypeInfo pnv_phb4_type_info = { } }; +static const TypeInfo pnv_phb5_type_info = { + .name = TYPE_PNV_PHB5, + .parent = TYPE_PNV_PHB4, + .instance_size = sizeof(PnvPHB4), +}; + static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data) { BusClass *k = BUS_CLASS(klass); @@ -1907,6 +1913,7 @@ static void pnv_phb4_register_types(void) type_register_static(&pnv_phb5_root_port_info); type_register_static(&pnv_phb4_root_port_info); type_register_static(&pnv_phb4_type_info); + type_register_static(&pnv_phb5_type_info); type_register_static(&pnv_phb4_iommu_memory_region_info); } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 0ab36e9c8f..a0dfa77c84 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -116,7 +116,8 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, int stack_no, Error **errp) { - PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), @@ -131,9 +132,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, } /* Add a single Root port if running with defaults */ - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), - PNV_PHB4_PEC_GET_CLASS(pec)->rp_model); - + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); } static void pnv_pec_realize(DeviceState *dev, Error **errp) @@ -265,6 +264,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB4_VERSION; + pecc->phb_type = TYPE_PNV_PHB4; pecc->num_phbs = pnv_pec_num_phbs; pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT; } @@ -317,6 +317,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB5_VERSION; + pecc->phb_type = TYPE_PNV_PHB5; pecc->num_phbs = pnv_phb5_pec_num_stacks; pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT; } diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index fbcf5bfb55..b02ecdceaa 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -203,6 +203,7 @@ struct PnvPhb4PecClass { const char *stk_compat; int stk_compat_size; uint64_t version; + const char *phb_type; const uint32_t *num_phbs; const char *rp_model; }; @@ -211,6 +212,10 @@ struct PnvPhb4PecClass { * POWER10 definitions */ +#define TYPE_PNV_PHB5 "pnv-phb5" +#define PNV_PHB5(obj) \ + OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5) + #define PNV_PHB5_VERSION 0x000000a500000001ull #define PNV_PHB5_DEVICE_ID 0x0652 From 8e6f45cc3f94d5a1ba5cf0017bc846454b3d3fa3 Mon Sep 17 00:00:00 2001 From: Frederic Barrat Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 19/20] ppc/pnv: Always create the PHB5 PEC devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Always create the PECs (PCI Express Controller) for the system. The PECs host the PHBs and we try to find the matching PEC when creating a PHB, so it must exist. It also matches what we do on POWER9 Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater [ clg: - Rewored commit log - Removed dynamic PHB5 ] Message-Id: <20220310155101.294568-3-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0ac86e104f..e7cd8b62ca 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1600,9 +1600,7 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); - if (defaults_enabled()) { - chip->num_pecs = pcc->num_pecs; - } + chip->num_pecs = pcc->num_pecs; for (i = 0; i < chip->num_pecs; i++) { object_initialize_child(obj, "pec[*]", &chip10->pecs[i], From 9c10d86fee11d96274ea6f7cda12d2471abe3c47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 14 Mar 2022 15:57:17 +0100 Subject: [PATCH 20/20] ppc/pnv: Remove user-created PHB{3,4,5} devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On a real system with POWER{8,9,10} processors, PHBs are sub-units of the processor, they can be deactivated by firmware but not plugged in or out like a PCI adapter on a slot. Nevertheless, having user-created PHBs in QEMU seemed to be a good idea for testing purposes : 1. having a limited set of PHBs speedups boot time. 2. it is useful to be able to mimic a partially broken topology you some time have to deal with during bring-up. PowerNV is also used for distro install tests and having libvirt support eases these tasks. libvirt prefers to run the machine with -nodefaults to be sure not to drag unexpected devices which would need to be defined in the domain file without being specified on the QEMU command line. For this reason : 3. -nodefaults should not include default PHBs User-created PHB{3,4,5} devices satisfied all these needs but reality proves to be a bit more complex, internally when modeling such devices, and externally when dealing with the user interface. Req 1. and 2. can be simply addressed differently with a machine option: "phb-mask=", which QEMU would use to enable/disable PHB device nodes when creating the device tree. For Req 3., we need to make sure we are taking the right approach. It seems that we should expose a new type of user-created PHB device, a generic virtualized one, that libvirt would use and not one depending on the processor revision. This needs more thinking. For now, remove user-created PHB{3,4,5} devices. All the cleanups we did are not lost and they will be useful for the next steps. Fixes: 5bc67b052b51 ("ppc/pnv: Introduce user creatable pnv-phb4 devices") Fixes: 1f6a88fffc75 ("ppc/pnv: Introduce support for user created PHB3 devices") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20220314130514.529931-1-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3.c | 33 ++------------------ hw/pci-host/pnv_phb4.c | 62 ++------------------------------------ hw/pci-host/pnv_phb4_pec.c | 7 ++--- hw/ppc/pnv.c | 25 +-------------- include/hw/ppc/pnv.h | 1 - 5 files changed, 10 insertions(+), 118 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index aafd46b635..ac801ac835 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -994,30 +994,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; - /* User created devices */ - if (!phb->chip) { - Error *local_err = NULL; - BusState *s; - - phb->chip = pnv_get_chip(pnv, phb->chip_id); - if (!phb->chip) { - error_setg(errp, "invalid chip id: %d", phb->chip_id); - return; - } - - /* - * Reparent user created devices to the chip to build - * correctly the device tree. - */ - pnv_chip_parent_fixup(phb->chip, OBJECT(phb), phb->phb_id); - - s = qdev_get_parent_bus(DEVICE(phb->chip)); - if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { - error_propagate(errp, local_err); - return; - } - } - if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; @@ -1077,10 +1053,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb); - if (defaults_enabled()) { - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), - TYPE_PNV_PHB3_ROOT_PORT); - } + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB3_ROOT_PORT); } void pnv_phb3_update_regions(PnvPHB3 *phb) @@ -1131,7 +1104,7 @@ static void pnv_phb3_class_init(ObjectClass *klass, void *data) dc->realize = pnv_phb3_realize; device_class_set_props(dc, pnv_phb3_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = true; + dc->user_creatable = false; } static const TypeInfo pnv_phb3_type_info = { @@ -1201,7 +1174,7 @@ static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) device_class_set_parent_realize(dc, pnv_phb3_root_port_realize, &rpc->parent_realize); - dc->user_creatable = true; + dc->user_creatable = false; k->vendor_id = PCI_VENDOR_ID_IBM; k->device_id = 0x03dc; diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index d1a911f988..b301762093 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1545,70 +1545,14 @@ static void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } -static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, - Error **errp) -{ - Pnv9Chip *chip9 = PNV9_CHIP(chip); - int chip_id = phb->chip_id; - int index = phb->phb_id; - int i, j; - - for (i = 0; i < chip->num_pecs; i++) { - /* - * For each PEC, check the amount of phbs it supports - * and see if the given phb4 index matches an index. - */ - PnvPhb4PecState *pec = &chip9->pecs[i]; - - for (j = 0; j < pec->num_phbs; j++) { - if (index == pnv_phb4_pec_get_phb_id(pec, j)) { - return pec; - } - } - } - - error_setg(errp, - "pnv-phb4 chip-id %d index %d didn't match any existing PEC", - chip_id, index); - - return NULL; -} - static void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB4 *phb = PNV_PHB4(dev); - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); PCIHostState *pci = PCI_HOST_BRIDGE(dev); XiveSource *xsrc = &phb->xsrc; - BusState *s; - Error *local_err = NULL; int nr_irqs; char name[32]; - if (!chip) { - error_setg(errp, "invalid chip id: %d", phb->chip_id); - return; - } - - /* User created PHBs need to be assigned to a PEC */ - if (!phb->pec) { - phb->pec = pnv_phb4_get_pec(chip, phb, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - } - - /* Reparent the PHB to the chip to build the device tree */ - pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id); - - s = qdev_get_parent_bus(DEVICE(chip)); - if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { - error_propagate(errp, local_err); - return; - } - /* Set the "big_phb" flag */ phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3; @@ -1766,7 +1710,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) dc->realize = pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = true; + dc->user_creatable = false; xfc->notify = pnv_phb4_xive_notify; } @@ -1864,7 +1808,7 @@ static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data) PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); dc->desc = "IBM PHB4 PCIE Root Port"; - dc->user_creatable = true; + dc->user_creatable = false; device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, &rpc->parent_realize); @@ -1894,7 +1838,7 @@ static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); dc->desc = "IBM PHB5 PCIE Root Port"; - dc->user_creatable = true; + dc->user_creatable = false; k->vendor_id = PCI_VENDOR_ID_IBM; k->device_id = PNV_PHB5_DEVICE_ID; diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index a0dfa77c84..6f1121a948 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -120,6 +120,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); + object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), &error_abort); object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id, @@ -150,10 +151,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) pec->num_phbs = pecc->num_phbs[pec->index]; /* Create PHBs if running with defaults */ - if (defaults_enabled()) { - for (i = 0; i < pec->num_phbs; i++) { - pnv_pec_default_phb_realize(pec, i, errp); - } + for (i = 0; i < pec->num_phbs; i++) { + pnv_pec_default_phb_realize(pec, i, errp); } /* Initialize the XSCOM regions for the PEC registers */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e7cd8b62ca..00f57c9678 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1141,9 +1141,7 @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); - if (defaults_enabled()) { - chip8->num_phbs = pcc->num_phbs; - } + chip8->num_phbs = pcc->num_phbs; for (i = 0; i < chip8->num_phbs; i++) { object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); @@ -1974,23 +1972,6 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) return NULL; } -void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index) -{ - Object *parent = OBJECT(chip); - g_autofree char *default_id = - g_strdup_printf("%s[%d]", object_get_typename(obj), index); - - if (obj->parent == parent) { - return; - } - - object_ref(obj); - object_unparent(obj); - object_property_add_child( - parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj); - object_unref(obj); -} - PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) { int i; @@ -2130,8 +2111,6 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); - - machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB3); } static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) @@ -2150,8 +2129,6 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); pmc->dt_power_mgt = pnv_dt_power_mgt; - - machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4); } static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 1e34ddd502..86cb7d7f97 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -190,7 +190,6 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); -void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index); #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") typedef struct PnvMachineClass PnvMachineClass;