suppressed explicit access type and use the exception routine to infer it from the micro operation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@529 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -153,6 +153,8 @@ typedef struct CPUPPCState {
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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int access_type; /* when a memory exception occurs, the access
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type is stored here */
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uint32_t exceptions; /* exception queue */
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uint32_t errors[16];
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int user_mode_only; /* user mode only simulation */
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@ -512,7 +512,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
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// printf("%s 0\n", __func__);
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is_user = flags & 0x01;
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access_type = flags & ~0x01;
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access_type = env->access_type;
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if (env->user_mode_only) {
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/* user mode only emulation */
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ret = -1;
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@ -8,14 +8,14 @@ void glue(do_lsw, MEMSUFFIX) (int dst)
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__func__, T0, T1, dst);
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}
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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ugpr(dst++) = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_INT);
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ugpr(dst++) = glue(ldl, MEMSUFFIX)((void *)T0);
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if (dst == 32)
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dst = 0;
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}
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if (T1 > 0) {
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
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tmp |= glue(_ldub, MEMSUFFIX)((void *)T0, ACCESS_INT) << sh;
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tmp |= glue(ldub, MEMSUFFIX)((void *)T0) << sh;
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}
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ugpr(dst) = tmp;
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}
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@ -30,14 +30,13 @@ void glue(do_stsw, MEMSUFFIX) (int src)
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__func__, T0, T1, src);
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}
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for (; T1 > 3; T1 -= 4, T0 += 4) {
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glue(_stl, MEMSUFFIX)((void *)T0, ugpr(src++), ACCESS_INT);
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glue(stl, MEMSUFFIX)((void *)T0, ugpr(src++));
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if (src == 32)
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src = 0;
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}
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if (T1 > 0) {
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
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glue(_stb, MEMSUFFIX)((void *)T0, (ugpr(src) >> sh) & 0xFF,
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ACCESS_INT);
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glue(stb, MEMSUFFIX)((void *)T0, (ugpr(src) >> sh) & 0xFF);
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}
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}
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@ -2,68 +2,62 @@
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void glue(do_lsw, MEMSUFFIX) (int dst);
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void glue(do_stsw, MEMSUFFIX) (int src);
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/* Internal helpers for sign extension and byte-reverse */
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static inline uint32_t glue(_ld16x, MEMSUFFIX) (void *EA, int type)
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static inline uint16_t glue(ld16r, MEMSUFFIX) (void *EA)
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{
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return s_ext16(glue(_lduw, MEMSUFFIX)(EA, type));
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}
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static inline uint16_t glue(_ld16r, MEMSUFFIX) (void *EA, int type)
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{
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uint16_t tmp = glue(_lduw, MEMSUFFIX)(EA, type);
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uint16_t tmp = glue(lduw, MEMSUFFIX)(EA);
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return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
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}
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static inline uint32_t glue(_ld32r, MEMSUFFIX) (void *EA, int type)
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static inline uint32_t glue(ld32r, MEMSUFFIX) (void *EA)
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{
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uint32_t tmp = glue(_ldl, MEMSUFFIX)(EA, type);
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uint32_t tmp = glue(ldl, MEMSUFFIX)(EA);
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return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) |
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((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
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}
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static inline void glue(_st16r, MEMSUFFIX) (void *EA, uint16_t data, int type)
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static inline void glue(st16r, MEMSUFFIX) (void *EA, uint16_t data)
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{
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uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8);
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glue(_stw, MEMSUFFIX)(EA, tmp, type);
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glue(stw, MEMSUFFIX)(EA, tmp);
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}
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static inline void glue(_st32r, MEMSUFFIX) (void *EA, uint32_t data, int type)
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static inline void glue(st32r, MEMSUFFIX) (void *EA, uint32_t data)
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{
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uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) |
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((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24);
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glue(_stl, MEMSUFFIX)(EA, tmp, type);
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glue(stl, MEMSUFFIX)(EA, tmp);
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}
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/*** Integer load ***/
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#define PPC_LD_OP(name, op) \
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PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
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{ \
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T1 = glue(op, MEMSUFFIX)((void *)T0, ACCESS_INT); \
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T1 = glue(op, MEMSUFFIX)((void *)T0); \
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RETURN(); \
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}
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#define PPC_ST_OP(name, op) \
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PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
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{ \
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glue(op, MEMSUFFIX)((void *)T0, T1, ACCESS_INT); \
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glue(op, MEMSUFFIX)((void *)T0, T1); \
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RETURN(); \
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}
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PPC_LD_OP(bz, _ldub);
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PPC_LD_OP(ha, _ld16x);
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PPC_LD_OP(hz, _lduw);
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PPC_LD_OP(wz, _ldl);
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PPC_LD_OP(bz, ldub);
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PPC_LD_OP(ha, ldsw);
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PPC_LD_OP(hz, lduw);
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PPC_LD_OP(wz, ldl);
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/*** Integer store ***/
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PPC_ST_OP(b, _stb);
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PPC_ST_OP(h, _stw);
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PPC_ST_OP(w, _stl);
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PPC_ST_OP(b, stb);
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PPC_ST_OP(h, stw);
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PPC_ST_OP(w, stl);
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/*** Integer load and store with byte reverse ***/
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PPC_LD_OP(hbr, _ld16r);
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PPC_LD_OP(wbr, _ld32r);
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PPC_ST_OP(hbr, _st16r);
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PPC_ST_OP(wbr, _st32r);
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PPC_LD_OP(hbr, ld16r);
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PPC_LD_OP(wbr, ld32r);
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PPC_ST_OP(hbr, st16r);
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PPC_ST_OP(wbr, st32r);
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/*** Integer load and store multiple ***/
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PPC_OP(glue(lmw, MEMSUFFIX))
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@ -71,7 +65,7 @@ PPC_OP(glue(lmw, MEMSUFFIX))
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int dst = PARAM(1);
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for (; dst < 32; dst++, T0 += 4) {
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ugpr(dst) = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_INT);
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ugpr(dst) = glue(ldl, MEMSUFFIX)((void *)T0);
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}
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RETURN();
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}
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@ -81,7 +75,7 @@ PPC_OP(glue(stmw, MEMSUFFIX))
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int src = PARAM(1);
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for (; src < 32; src++, T0 += 4) {
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glue(_stl, MEMSUFFIX)((void *)T0, ugpr(src), ACCESS_INT);
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glue(stl, MEMSUFFIX)((void *)T0, ugpr(src));
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}
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RETURN();
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}
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@ -150,7 +144,7 @@ PPC_OP(glue(stwcx, MEMSUFFIX))
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if (regs->reserve != T0) {
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env->crf[0] = xer_ov;
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} else {
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glue(_stl, MEMSUFFIX)((void *)T0, T1, ACCESS_RES);
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glue(stl, MEMSUFFIX)((void *)T0, T1);
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env->crf[0] = xer_ov | 0x02;
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}
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}
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@ -160,27 +154,27 @@ PPC_OP(glue(stwcx, MEMSUFFIX))
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PPC_OP(glue(dcbz, MEMSUFFIX))
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{
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x00), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x04), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x08), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x0C), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x10), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x14), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x18), 0, ACCESS_INT);
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glue(_stl, MEMSUFFIX)((void *)(T0 + 0x1C), 0, ACCESS_INT);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x00), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x04), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x08), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x0C), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x10), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x14), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x18), 0);
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glue(stl, MEMSUFFIX)((void *)(T0 + 0x1C), 0);
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RETURN();
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}
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/* External access */
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PPC_OP(glue(eciwx, MEMSUFFIX))
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{
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T1 = glue(_ldl, MEMSUFFIX)((void *)T0, ACCESS_EXT);
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T1 = glue(ldl, MEMSUFFIX)((void *)T0);
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RETURN();
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}
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PPC_OP(glue(ecowx, MEMSUFFIX))
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{
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glue(_stl, MEMSUFFIX)((void *)T0, T1, ACCESS_EXT);
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glue(stl, MEMSUFFIX)((void *)T0, T1);
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RETURN();
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}
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