target/ppc: Implement vextsd2q
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-9-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -426,6 +426,7 @@ VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb
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VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
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VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
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VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb
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VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb
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VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb
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VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb
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VEXTSD2Q 000100 ..... 11011 ..... 11000000010 @VX_tb
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## Vector Mask Manipulation Instructions
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## Vector Mask Manipulation Instructions
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@ -1825,6 +1825,24 @@ TRANS(VEXTSB2D, do_vexts, MO_64, 56);
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TRANS(VEXTSH2D, do_vexts, MO_64, 48);
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TRANS(VEXTSH2D, do_vexts, MO_64, 48);
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TRANS(VEXTSW2D, do_vexts, MO_64, 32);
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TRANS(VEXTSW2D, do_vexts, MO_64, 32);
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static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
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{
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TCGv_i64 tmp;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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tmp = tcg_temp_new_i64();
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get_avr64(tmp, a->vrb, false);
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set_avr64(a->vrt, tmp, false);
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tcg_gen_sari_i64(tmp, tmp, 63);
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set_avr64(a->vrt, tmp, true);
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tcg_temp_free_i64(tmp);
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return true;
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}
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GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
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GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
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GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
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GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
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GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
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GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
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