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target-mips: generate a reserved instruction exception on CPU without DSP 

On CPU without DSP ASE support, a reserved instruction exception (instead of
a DSP ASE sate disabled) should be generated.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2013-01-01 18:02:23 +01:00
parent d75c135e6b
commit ad153f153d
1 changed files with 10 additions and 2 deletions
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12
target-mips/translate.c
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@ -1394,14 +1394,22 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs)
static inline void check_dsp(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
generate_exception(ctx, EXCP_DSPDIS);
if (ctx->insn_flags & ASE_DSP) {
generate_exception(ctx, EXCP_DSPDIS);
} else {
generate_exception(ctx, EXCP_RI);
}
}
}
static inline void check_dspr2(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
generate_exception(ctx, EXCP_DSPDIS);
if (ctx->insn_flags & ASE_DSP) {
generate_exception(ctx, EXCP_DSPDIS);
} else {
generate_exception(ctx, EXCP_RI);
}
}
}