host/include/loongarch64: Add atomic16 load and store
While loongarch64 does not have a 128-bit cmpxchg, it does have 128-bit atomic load and store via the vector unit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-6-richard.henderson@linaro.org>
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host/include/loongarch64/host/atomic128-ldst.h
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host/include/loongarch64/host/atomic128-ldst.h
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Load/store for 128-bit atomic operations, LoongArch version.
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*
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* See docs/devel/atomics.rst for discussion about the guarantees each
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* atomic primitive is meant to provide.
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*/
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#ifndef LOONGARCH_ATOMIC128_LDST_H
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#define LOONGARCH_ATOMIC128_LDST_H
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#include "host/cpuinfo.h"
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#include "tcg/debug-assert.h"
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#define HAVE_ATOMIC128_RO likely(cpuinfo & CPUINFO_LSX)
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#define HAVE_ATOMIC128_RW HAVE_ATOMIC128_RO
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/*
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* As of gcc 13 and clang 16, there is no compiler support for LSX at all.
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* Use inline assembly throughout.
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*/
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static inline Int128 atomic16_read_ro(const Int128 *ptr)
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{
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uint64_t l, h;
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tcg_debug_assert(HAVE_ATOMIC128_RO);
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asm("vld $vr0, %2, 0\n\t"
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"vpickve2gr.d %0, $vr0, 0\n\t"
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"vpickve2gr.d %1, $vr0, 1"
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: "=r"(l), "=r"(h) : "r"(ptr), "m"(*ptr) : "f0");
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return int128_make128(l, h);
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}
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static inline Int128 atomic16_read_rw(Int128 *ptr)
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{
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return atomic16_read_ro(ptr);
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}
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static inline void atomic16_set(Int128 *ptr, Int128 val)
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{
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uint64_t l = int128_getlo(val), h = int128_gethi(val);
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tcg_debug_assert(HAVE_ATOMIC128_RW);
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asm("vinsgr2vr.d $vr0, %1, 0\n\t"
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"vinsgr2vr.d $vr0, %2, 1\n\t"
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"vst $vr0, %3, 0"
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: "=m"(*ptr) : "r"(l), "r"(h), "r"(ptr) : "f0");
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}
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#endif /* LOONGARCH_ATOMIC128_LDST_H */
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host/include/loongarch64/host/load-extract-al16-al8.h
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host/include/loongarch64/host/load-extract-al16-al8.h
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Atomic extract 64 from 128-bit, LoongArch version.
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*
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* Copyright (C) 2023 Linaro, Ltd.
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*/
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#ifndef LOONGARCH_LOAD_EXTRACT_AL16_AL8_H
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#define LOONGARCH_LOAD_EXTRACT_AL16_AL8_H
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#include "host/cpuinfo.h"
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#include "tcg/debug-assert.h"
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/**
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* load_atom_extract_al16_or_al8:
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* @pv: host address
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* @s: object size in bytes, @s <= 8.
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*
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* Load @s bytes from @pv, when pv % s != 0. If [p, p+s-1] does not
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* cross an 16-byte boundary then the access must be 16-byte atomic,
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* otherwise the access must be 8-byte atomic.
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*/
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static inline uint64_t load_atom_extract_al16_or_al8(void *pv, int s)
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{
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uintptr_t pi = (uintptr_t)pv;
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Int128 *ptr_align = (Int128 *)(pi & ~7);
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int shr = (pi & 7) * 8;
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uint64_t l, h;
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tcg_debug_assert(HAVE_ATOMIC128_RO);
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asm("vld $vr0, %2, 0\n\t"
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"vpickve2gr.d %0, $vr0, 0\n\t"
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"vpickve2gr.d %1, $vr0, 1"
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: "=r"(l), "=r"(h) : "r"(ptr_align), "m"(*ptr_align) : "f0");
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return (l >> shr) | (h << (-shr & 63));
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}
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#endif /* LOONGARCH_LOAD_EXTRACT_AL16_AL8_H */
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host/include/loongarch64/host/store-insert-al16.h
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host/include/loongarch64/host/store-insert-al16.h
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Atomic store insert into 128-bit, LoongArch version.
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*/
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#ifndef LOONGARCH_STORE_INSERT_AL16_H
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#define LOONGARCH_STORE_INSERT_AL16_H
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void store_atom_insert_al16(Int128 *ps, Int128 val, Int128 msk)
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QEMU_ERROR("unsupported atomic");
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#endif /* LOONGARCH_STORE_INSERT_AL16_H */
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