ppc queue:
* PNV I2C fixes * VSX instruction fix when converting floating point to integer values -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmVcZ18ACgkQUaNDx8/7 7KG1GBAAopdIWc33pY1kaJlHxXDDtTxShWT384r62unPO0vaDtvmlLBvD0kTRIzk E6OcWeGS/L2D03nI127o5Y677koL20TlOpsR4fZdOwbQUSSVTMsLN5m8Rqvu4Ptx zA8t/Oio+RTxkZ1SHRuEQNC5EWzFklm5R95zyvLEAbMdJ44thlXyo9KgWe8XoBBV tkreEzWvv4F4Nf7nZYnxvOIHsi/8No0bMMjBNGC/v+svpayuaWmsCP4/4vmVRYRP 28R6uMooo9xu0X6oBzqbAV6y6XFSP8pwsvVPd1yAbFhS3w2qw18VpWoMUl2UkVGx ZNNHjt3HPtGAEtnWAdvzVS8sFi929pHf2v5/h8gEhfZ2e4NVS1zJj3K3OqJgWfEB XjiIO4NF4gnbXKIlvZX8m5RqdtxbdKx7BVmJtlzJd7IDERRLe0cNSCZ06s/GcICi AHtxhyA5GGWs2HDQwkOimwDOholjjVbz/sIcHLCpm/jyxcdk9VwE6hBO/9nTcntg IaQ/kWHlbQgTNXNuFDBwiOMuEQ5G4bb6sdqH+CWZU/owFqgXHIlki7oneX6SB09T GUyVwScLWlspCJRpX/y4ubyfGB3ZqAQ9REita4YIMveDvNU83LS344MRrBpzQ+ZI 1yCoHdBsNUkpr9dN/uwkjDSBlDoyWJ2TAgQHsprNUD04ChML7Fs= =qx4p -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20231121' of https://github.com/legoater/qemu into staging ppc queue: * PNV I2C fixes * VSX instruction fix when converting floating point to integer values # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmVcZ18ACgkQUaNDx8/7 # 7KG1GBAAopdIWc33pY1kaJlHxXDDtTxShWT384r62unPO0vaDtvmlLBvD0kTRIzk # E6OcWeGS/L2D03nI127o5Y677koL20TlOpsR4fZdOwbQUSSVTMsLN5m8Rqvu4Ptx # zA8t/Oio+RTxkZ1SHRuEQNC5EWzFklm5R95zyvLEAbMdJ44thlXyo9KgWe8XoBBV # tkreEzWvv4F4Nf7nZYnxvOIHsi/8No0bMMjBNGC/v+svpayuaWmsCP4/4vmVRYRP # 28R6uMooo9xu0X6oBzqbAV6y6XFSP8pwsvVPd1yAbFhS3w2qw18VpWoMUl2UkVGx # ZNNHjt3HPtGAEtnWAdvzVS8sFi929pHf2v5/h8gEhfZ2e4NVS1zJj3K3OqJgWfEB # XjiIO4NF4gnbXKIlvZX8m5RqdtxbdKx7BVmJtlzJd7IDERRLe0cNSCZ06s/GcICi # AHtxhyA5GGWs2HDQwkOimwDOholjjVbz/sIcHLCpm/jyxcdk9VwE6hBO/9nTcntg # IaQ/kWHlbQgTNXNuFDBwiOMuEQ5G4bb6sdqH+CWZU/owFqgXHIlki7oneX6SB09T # GUyVwScLWlspCJRpX/y4ubyfGB3ZqAQ9REita4YIMveDvNU83LS344MRrBpzQ+ZI # 1yCoHdBsNUkpr9dN/uwkjDSBlDoyWJ2TAgQHsprNUD04ChML7Fs= # =qx4p # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Nov 2023 03:16:31 EST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20231121' of https://github.com/legoater/qemu: ppc/pnv: Fix PNV I2C invalid status after reset ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses target/ppc: Fix bugs in VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros ppc/pnv: Fix potential overflow in I2C model Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
adf798b379
@ -1623,7 +1623,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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return;
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}
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pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE +
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chip9->i2c[i].engine * PNV9_XSCOM_I2CM_SIZE,
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(chip9->i2c[i].engine - 1) *
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PNV9_XSCOM_I2CM_SIZE,
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&chip9->i2c[i].xscom_regs);
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qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0,
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qdev_get_gpio_in(DEVICE(&chip9->psi),
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@ -1871,7 +1872,8 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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return;
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}
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE +
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chip10->i2c[i].engine * PNV10_XSCOM_I2CM_SIZE,
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(chip10->i2c[i].engine - 1) *
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PNV10_XSCOM_I2CM_SIZE,
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&chip10->i2c[i].xscom_regs);
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qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0,
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qdev_get_gpio_in(DEVICE(&chip10->psi),
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@ -151,6 +151,7 @@
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#define I2C_RESET_S_SDA_REG 0x11
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#define PNV_I2C_FIFO_SIZE 8
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#define PNV_I2C_MAX_BUSSES 64
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static I2CBus *pnv_i2c_get_bus(PnvI2C *i2c)
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{
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@ -437,7 +438,7 @@ static uint64_t pnv_i2c_xscom_read(void *opaque, hwaddr addr,
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case I2C_PORT_BUSY_REG: /* compute busy bit for each port */
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val = 0;
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for (i = 0; i < i2c->num_busses; i++) {
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val |= i2c_bus_busy(i2c->busses[i]) << i;
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val |= (uint64_t)i2c_bus_busy(i2c->busses[i]) << i;
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}
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break;
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@ -462,6 +463,23 @@ static uint64_t pnv_i2c_xscom_read(void *opaque, hwaddr addr,
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return val;
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}
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static void pnv_i2c_reset(void *dev)
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{
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PnvI2C *i2c = PNV_I2C(dev);
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memset(i2c->regs, 0, sizeof(i2c->regs));
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i2c->regs[I2C_STAT_REG] =
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SETFIELD(I2C_STAT_UPPER_THRS, 0ull, i2c->num_busses - 1) |
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I2C_STAT_CMD_COMP | I2C_STAT_SCL_INPUT_LEVEL |
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I2C_STAT_SDA_INPUT_LEVEL;
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i2c->regs[I2C_EXTD_STAT_REG] =
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SETFIELD(I2C_EXTD_STAT_FIFO_SIZE, 0ull, PNV_I2C_FIFO_SIZE) |
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SETFIELD(I2C_EXTD_STAT_I2C_VERSION, 0ull, 23); /* last version */
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fifo8_reset(&i2c->fifo);
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}
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static void pnv_i2c_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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@ -499,16 +517,7 @@ static void pnv_i2c_xscom_write(void *opaque, hwaddr addr,
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break;
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case I2C_RESET_I2C_REG:
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i2c->regs[I2C_MODE_REG] = 0;
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i2c->regs[I2C_CMD_REG] = 0;
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i2c->regs[I2C_WATERMARK_REG] = 0;
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i2c->regs[I2C_INTR_MASK_REG] = 0;
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i2c->regs[I2C_INTR_COND_REG] = 0;
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i2c->regs[I2C_INTR_RAW_COND_REG] = 0;
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i2c->regs[I2C_STAT_REG] = 0;
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i2c->regs[I2C_RESIDUAL_LEN_REG] = 0;
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i2c->regs[I2C_EXTD_STAT_REG] &=
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(I2C_EXTD_STAT_FIFO_SIZE | I2C_EXTD_STAT_I2C_VERSION);
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pnv_i2c_reset(i2c);
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break;
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case I2C_RESET_ERRORS:
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@ -593,7 +602,7 @@ static int pnv_i2c_dt_xscom(PnvXScomInterface *dev, void *fdt,
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int i2c_offset;
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const char i2c_compat[] = "ibm,power8-i2cm\0ibm,power9-i2cm";
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uint32_t i2c_pcba = PNV9_XSCOM_I2CM_BASE +
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i2c->engine * PNV9_XSCOM_I2CM_SIZE;
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(i2c->engine - 1) * PNV9_XSCOM_I2CM_SIZE;
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uint32_t reg[2] = {
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cpu_to_be32(i2c_pcba),
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cpu_to_be32(PNV9_XSCOM_I2CM_SIZE)
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@ -620,20 +629,6 @@ static int pnv_i2c_dt_xscom(PnvXScomInterface *dev, void *fdt,
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return 0;
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}
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static void pnv_i2c_reset(void *dev)
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{
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PnvI2C *i2c = PNV_I2C(dev);
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memset(i2c->regs, 0, sizeof(i2c->regs));
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i2c->regs[I2C_STAT_REG] = I2C_STAT_CMD_COMP;
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i2c->regs[I2C_EXTD_STAT_REG] =
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SETFIELD(I2C_EXTD_STAT_FIFO_SIZE, 0ull, PNV_I2C_FIFO_SIZE) |
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SETFIELD(I2C_EXTD_STAT_I2C_VERSION, 0ull, 23); /* last version */
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fifo8_reset(&i2c->fifo);
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}
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static void pnv_i2c_realize(DeviceState *dev, Error **errp)
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{
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PnvI2C *i2c = PNV_I2C(dev);
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@ -641,6 +636,11 @@ static void pnv_i2c_realize(DeviceState *dev, Error **errp)
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assert(i2c->chip);
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if (i2c->num_busses > PNV_I2C_MAX_BUSSES) {
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error_setg(errp, "Invalid number of busses: %u", i2c->num_busses);
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return;
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}
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pnv_xscom_region_init(&i2c->xscom_regs, OBJECT(i2c), &pnv_i2c_xscom_ops,
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i2c, "xscom-i2c", PNV9_XSCOM_I2CM_SIZE);
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@ -2880,20 +2880,22 @@ uint64_t helper_XSCVSPDPN(uint64_t xb)
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#define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, sfi, rnan) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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{ \
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int all_flags = 0; \
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ppc_vsr_t t = { }; \
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int i, flags; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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helper_reset_fpstatus(env); \
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t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
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flags = env->fp_status.float_exception_flags; \
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all_flags |= flags; \
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if (unlikely(flags & float_flag_invalid)) { \
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t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
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} \
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} \
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\
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*xt = t; \
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env->fp_status.float_exception_flags = all_flags; \
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do_float_check_status(env, sfi, GETPC()); \
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}
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@ -2945,15 +2947,16 @@ VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
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#define VSX_CVT_FP_TO_INT2(op, nels, stp, ttp, sfi, rnan) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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{ \
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int all_flags = 0; \
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ppc_vsr_t t = { }; \
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int i, flags; \
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\
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helper_reset_fpstatus(env); \
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\
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for (i = 0; i < nels; i++) { \
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helper_reset_fpstatus(env); \
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t.VsrW(2 * i) = stp##_to_##ttp##_round_to_zero(xb->VsrD(i), \
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&env->fp_status); \
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flags = env->fp_status.float_exception_flags; \
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all_flags |= flags; \
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if (unlikely(flags & float_flag_invalid)) { \
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t.VsrW(2 * i) = float_invalid_cvt(env, flags, t.VsrW(2 * i), \
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rnan, 0, GETPC()); \
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@ -2962,6 +2965,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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} \
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\
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*xt = t; \
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env->fp_status.float_exception_flags = all_flags; \
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do_float_check_status(env, sfi, GETPC()); \
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}
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@ -16,6 +16,11 @@ PPC64_TESTS=bcdsub non_signalling_xscv
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endif
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$(PPC64_TESTS): CFLAGS += -mpower8-vector
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ifneq ($(CROSS_CC_HAS_POWER8_VECTOR),)
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PPC64_TESTS += vsx_f2i_nan
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endif
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vsx_f2i_nan: CFLAGS += -mpower8-vector -I$(SRC_PATH)/include
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PPC64_TESTS += mtfsf
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PPC64_TESTS += mffsce
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300
tests/tcg/ppc64/vsx_f2i_nan.c
Normal file
300
tests/tcg/ppc64/vsx_f2i_nan.c
Normal file
@ -0,0 +1,300 @@
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#include <stdio.h>
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#include "qemu/compiler.h"
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typedef vector float vsx_float32_vec_t;
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typedef vector double vsx_float64_vec_t;
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typedef vector signed int vsx_int32_vec_t;
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typedef vector unsigned int vsx_uint32_vec_t;
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typedef vector signed long long vsx_int64_vec_t;
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typedef vector unsigned long long vsx_uint64_vec_t;
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#define DEFINE_VSX_F2I_FUNC(SRC_T, DEST_T, INSN) \
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static inline vsx_##DEST_T##_vec_t \
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vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(vsx_##SRC_T##_vec_t v) \
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{ \
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vsx_##DEST_T##_vec_t result; \
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asm(#INSN " %x0, %x1" : "=wa" (result) : "wa" (v)); \
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return result; \
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}
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DEFINE_VSX_F2I_FUNC(float32, int32, xvcvspsxws)
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DEFINE_VSX_F2I_FUNC(float32, uint32, xvcvspuxws)
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DEFINE_VSX_F2I_FUNC(float32, int64, xvcvspsxds)
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DEFINE_VSX_F2I_FUNC(float32, uint64, xvcvspuxds)
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DEFINE_VSX_F2I_FUNC(float64, int32, xvcvdpsxws)
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DEFINE_VSX_F2I_FUNC(float64, uint32, xvcvdpuxws)
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DEFINE_VSX_F2I_FUNC(float64, int64, xvcvdpsxds)
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DEFINE_VSX_F2I_FUNC(float64, uint64, xvcvdpuxds)
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static inline vsx_float32_vec_t vsx_float32_is_nan(vsx_float32_vec_t v)
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{
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vsx_float32_vec_t abs_v;
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vsx_float32_vec_t result_mask;
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const vsx_uint32_vec_t f32_pos_inf_bits = {0x7F800000U, 0x7F800000U,
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0x7F800000U, 0x7F800000U};
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asm("xvabssp %x0, %x1" : "=wa" (abs_v) : "wa" (v));
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asm("vcmpgtuw %0, %1, %2"
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: "=v" (result_mask)
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: "v" (abs_v), "v" (f32_pos_inf_bits));
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return result_mask;
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}
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static inline vsx_float64_vec_t vsx_float64_is_nan(vsx_float64_vec_t v)
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{
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vsx_float64_vec_t abs_v;
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vsx_float64_vec_t result_mask;
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const vsx_uint64_vec_t f64_pos_inf_bits = {0x7FF0000000000000ULL,
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0x7FF0000000000000ULL};
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asm("xvabsdp %x0, %x1" : "=wa" (abs_v) : "wa" (v));
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asm("vcmpgtud %0, %1, %2"
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: "=v" (result_mask)
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: "v" (abs_v), "v" (f64_pos_inf_bits));
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return result_mask;
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}
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#define DEFINE_VSX_BINARY_LOGICAL_OP_INSN(LANE_TYPE, OP_NAME, OP_INSN) \
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static inline vsx_##LANE_TYPE##_vec_t vsx_##LANE_TYPE##_##OP_NAME( \
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vsx_##LANE_TYPE##_vec_t a, vsx_##LANE_TYPE##_vec_t b) \
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{ \
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vsx_##LANE_TYPE##_vec_t result; \
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asm(#OP_INSN " %x0, %x1, %x2" : "=wa" (result) : "wa" (a), "wa" (b)); \
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return result; \
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}
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int32, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint32, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint64, logical_and, xxland)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_andc, xxlandc)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_andc, xxlandc)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float32, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(float64, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int32, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint32, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(int64, logical_or, xxlor)
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DEFINE_VSX_BINARY_LOGICAL_OP_INSN(uint64, logical_or, xxlor)
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static inline vsx_int32_vec_t vsx_mask_out_float32_vec_to_int32_vec(
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vsx_int32_vec_t v)
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{
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return v;
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}
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static inline vsx_uint32_vec_t vsx_mask_out_float32_vec_to_uint32_vec(
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vsx_uint32_vec_t v)
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{
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return v;
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}
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static inline vsx_int64_vec_t vsx_mask_out_float32_vec_to_int64_vec(
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vsx_int64_vec_t v)
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{
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return v;
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}
|
||||
static inline vsx_uint64_vec_t vsx_mask_out_float32_vec_to_uint64_vec(
|
||||
vsx_uint64_vec_t v)
|
||||
{
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline vsx_int32_vec_t vsx_mask_out_float64_vec_to_int32_vec(
|
||||
vsx_int32_vec_t v)
|
||||
{
|
||||
#if HOST_BIG_ENDIAN
|
||||
const vsx_int32_vec_t valid_lanes_mask = {-1, 0, -1, 0};
|
||||
#else
|
||||
const vsx_int32_vec_t valid_lanes_mask = {0, -1, 0, -1};
|
||||
#endif
|
||||
|
||||
return vsx_int32_logical_and(v, valid_lanes_mask);
|
||||
}
|
||||
|
||||
static inline vsx_uint32_vec_t vsx_mask_out_float64_vec_to_uint32_vec(
|
||||
vsx_uint32_vec_t v)
|
||||
{
|
||||
return (vsx_uint32_vec_t)vsx_mask_out_float64_vec_to_int32_vec(
|
||||
(vsx_int32_vec_t)v);
|
||||
}
|
||||
|
||||
static inline vsx_int64_vec_t vsx_mask_out_float64_vec_to_int64_vec(
|
||||
vsx_int64_vec_t v)
|
||||
{
|
||||
return v;
|
||||
}
|
||||
static inline vsx_uint64_vec_t vsx_mask_out_float64_vec_to_uint64_vec(
|
||||
vsx_uint64_vec_t v)
|
||||
{
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline void print_vsx_float32_vec_elements(FILE *stream,
|
||||
vsx_float32_vec_t vec)
|
||||
{
|
||||
fprintf(stream, "%g, %g, %g, %g", (double)vec[0], (double)vec[1],
|
||||
(double)vec[2], (double)vec[3]);
|
||||
}
|
||||
|
||||
static inline void print_vsx_float64_vec_elements(FILE *stream,
|
||||
vsx_float64_vec_t vec)
|
||||
{
|
||||
fprintf(stream, "%.17g, %.17g", vec[0], vec[1]);
|
||||
}
|
||||
|
||||
static inline void print_vsx_int32_vec_elements(FILE *stream,
|
||||
vsx_int32_vec_t vec)
|
||||
{
|
||||
fprintf(stream, "%d, %d, %d, %d", vec[0], vec[1], vec[2], vec[3]);
|
||||
}
|
||||
|
||||
static inline void print_vsx_uint32_vec_elements(FILE *stream,
|
||||
vsx_uint32_vec_t vec)
|
||||
{
|
||||
fprintf(stream, "%u, %u, %u, %u", vec[0], vec[1], vec[2], vec[3]);
|
||||
}
|
||||
|
||||
static inline void print_vsx_int64_vec_elements(FILE *stream,
|
||||
vsx_int64_vec_t vec)
|
||||
{
|
||||
fprintf(stream, "%lld, %lld", vec[0], vec[1]);
|
||||
}
|
||||
|
||||
static inline void print_vsx_uint64_vec_elements(FILE *stream,
|
||||
vsx_uint64_vec_t vec)
|
||||
{
|
||||
fprintf(stream, "%llu, %llu", vec[0], vec[1]);
|
||||
}
|
||||
|
||||
#define DEFINE_VSX_ALL_EQ_FUNC(LANE_TYPE, CMP_INSN) \
|
||||
static inline int vsx_##LANE_TYPE##_all_eq(vsx_##LANE_TYPE##_vec_t a, \
|
||||
vsx_##LANE_TYPE##_vec_t b) \
|
||||
{ \
|
||||
unsigned result; \
|
||||
vsx_##LANE_TYPE##_vec_t is_eq_mask_vec; \
|
||||
asm(#CMP_INSN ". %0, %2, %3\n\t" \
|
||||
"mfocrf %1, 2" \
|
||||
: "=v" (is_eq_mask_vec), "=r" (result) \
|
||||
: "v" (a), "v" (b) \
|
||||
: "cr6"); \
|
||||
return (int)((result >> 7) & 1u); \
|
||||
}
|
||||
|
||||
DEFINE_VSX_ALL_EQ_FUNC(int32, vcmpequw)
|
||||
DEFINE_VSX_ALL_EQ_FUNC(uint32, vcmpequw)
|
||||
DEFINE_VSX_ALL_EQ_FUNC(int64, vcmpequd)
|
||||
DEFINE_VSX_ALL_EQ_FUNC(uint64, vcmpequd)
|
||||
|
||||
#define DEFINE_VSX_F2I_TEST_FUNC(SRC_T, DEST_T) \
|
||||
static inline int test_vsx_conv_##SRC_T##_vec_to_##DEST_T##_vec( \
|
||||
vsx_##SRC_T##_vec_t src_v) \
|
||||
{ \
|
||||
const vsx_##SRC_T##_vec_t is_nan_mask = vsx_##SRC_T##_is_nan(src_v); \
|
||||
const vsx_##SRC_T##_vec_t nan_src_v = \
|
||||
vsx_##SRC_T##_logical_and(src_v, is_nan_mask); \
|
||||
const vsx_##SRC_T##_vec_t non_nan_src_v = \
|
||||
vsx_##SRC_T##_logical_andc(src_v, is_nan_mask); \
|
||||
\
|
||||
const vsx_##DEST_T##_vec_t expected_result = \
|
||||
vsx_mask_out_##SRC_T##_vec_to_##DEST_T##_vec( \
|
||||
vsx_##DEST_T##_logical_or( \
|
||||
vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(nan_src_v), \
|
||||
vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec( \
|
||||
non_nan_src_v))); \
|
||||
const vsx_##DEST_T##_vec_t actual_result = \
|
||||
vsx_mask_out_##SRC_T##_vec_to_##DEST_T##_vec( \
|
||||
vsx_convert_##SRC_T##_vec_to_##DEST_T##_vec(src_v)); \
|
||||
const int test_result = \
|
||||
vsx_##DEST_T##_all_eq(expected_result, actual_result); \
|
||||
\
|
||||
if (unlikely(test_result == 0)) { \
|
||||
fputs("FAIL: Conversion of " #SRC_T " vector to " #DEST_T \
|
||||
" vector failed\n", stdout); \
|
||||
fputs("Source values: ", stdout); \
|
||||
print_vsx_##SRC_T##_vec_elements(stdout, src_v); \
|
||||
fputs("\nExpected result: ", stdout); \
|
||||
print_vsx_##DEST_T##_vec_elements(stdout, expected_result); \
|
||||
fputs("\nActual result: ", stdout); \
|
||||
print_vsx_##DEST_T##_vec_elements(stdout, actual_result); \
|
||||
fputs("\n\n", stdout); \
|
||||
} \
|
||||
\
|
||||
return test_result; \
|
||||
}
|
||||
|
||||
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float32, int32)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float32, uint32)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float32, int64)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float32, uint64)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float64, int32)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float64, uint32)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float64, int64)
|
||||
DEFINE_VSX_F2I_TEST_FUNC(float64, uint64)
|
||||
|
||||
static inline vsx_int32_vec_t vsx_int32_vec_from_mask(int mask)
|
||||
{
|
||||
const vsx_int32_vec_t bits_to_test = {1, 2, 4, 8};
|
||||
const vsx_int32_vec_t vec_mask = {mask, mask, mask, mask};
|
||||
vsx_int32_vec_t result;
|
||||
|
||||
asm("vcmpequw %0, %1, %2"
|
||||
: "=v" (result)
|
||||
: "v" (vsx_int32_logical_and(vec_mask, bits_to_test)),
|
||||
"v" (bits_to_test));
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline vsx_int64_vec_t vsx_int64_vec_from_mask(int mask)
|
||||
{
|
||||
const vsx_int64_vec_t bits_to_test = {1, 2};
|
||||
const vsx_int64_vec_t vec_mask = {mask, mask};
|
||||
vsx_int64_vec_t result;
|
||||
|
||||
asm("vcmpequd %0, %1, %2"
|
||||
: "=v" (result)
|
||||
: "v" (vsx_int64_logical_and(vec_mask, bits_to_test)),
|
||||
"v" (bits_to_test));
|
||||
return result;
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
const vsx_float32_vec_t f32_iota1 = {1.0f, 2.0f, 3.0f, 4.0f};
|
||||
const vsx_float64_vec_t f64_iota1 = {1.0, 2.0};
|
||||
|
||||
int num_of_tests_failed = 0;
|
||||
|
||||
for (int i = 0; i < 16; i++) {
|
||||
const vsx_int32_vec_t nan_mask = vsx_int32_vec_from_mask(i);
|
||||
const vsx_float32_vec_t f32_v =
|
||||
vsx_float32_logical_or(f32_iota1, (vsx_float32_vec_t)nan_mask);
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float32_vec_to_int32_vec(f32_v));
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float32_vec_to_int64_vec(f32_v));
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float32_vec_to_uint32_vec(f32_v));
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float32_vec_to_uint64_vec(f32_v));
|
||||
}
|
||||
|
||||
for (int i = 0; i < 4; i++) {
|
||||
const vsx_int64_vec_t nan_mask = vsx_int64_vec_from_mask(i);
|
||||
const vsx_float64_vec_t f64_v =
|
||||
vsx_float64_logical_or(f64_iota1, (vsx_float64_vec_t)nan_mask);
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float64_vec_to_int32_vec(f64_v));
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float64_vec_to_int64_vec(f64_v));
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float64_vec_to_uint32_vec(f64_v));
|
||||
num_of_tests_failed +=
|
||||
(int)(!test_vsx_conv_float64_vec_to_uint64_vec(f64_v));
|
||||
}
|
||||
|
||||
printf("%d tests failed\n", num_of_tests_failed);
|
||||
return (int)(num_of_tests_failed != 0);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user