Merge common ISA access routines.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2159 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook
parent
6787f5fae0
commit
aef445bd7e
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@ -289,7 +289,7 @@ ifeq ($(ARCH),alpha)
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endif
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# must use static linking to avoid leaving stuff in virtual address space
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VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o
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VL_OBJS=vl.o osdep.o readline.o monitor.o pci.o console.o loader.o isa_mmio.o
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VL_OBJS+=block.o block-raw.o
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VL_OBJS+=block-cow.o block-qcow.o aes.o block-vmdk.o block-cloop.o block-dmg.o block-bochs.o block-vpc.o block-vvfat.o block-qcow2.o
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ifdef CONFIG_WIN32
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@ -0,0 +1,102 @@
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/*
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* Memory mapped access to ISA IO space.
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outb(NULL, addr & 0xffff, val);
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}
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static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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cpu_outw(NULL, addr & 0xffff, val);
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}
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static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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cpu_outl(NULL, addr & 0xffff, val);
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}
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static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inb(NULL, addr & 0xffff);
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return val;
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}
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static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inw(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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return val;
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}
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static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inl(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *isa_mmio_write[] = {
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&isa_mmio_writeb,
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&isa_mmio_writew,
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&isa_mmio_writel,
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};
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static CPUReadMemoryFunc *isa_mmio_read[] = {
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&isa_mmio_readb,
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&isa_mmio_readw,
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&isa_mmio_readl,
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};
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static int isa_mmio_iomemtype = 0;
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
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{
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if (!isa_mmio_iomemtype) {
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isa_mmio_iomemtype = cpu_register_io_memory(0, isa_mmio_read,
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isa_mmio_write, NULL);
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}
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cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
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}
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@ -107,88 +107,6 @@ void cpu_mips_clock_init (CPUState *env)
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}
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static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#endif
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cpu_outb(NULL, addr & 0xffff, value);
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}
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static uint32_t io_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr & 0xffff);
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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#endif
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return ret;
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}
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static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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cpu_outw(NULL, addr & 0xffff, value);
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}
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static uint32_t io_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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#endif
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return ret;
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}
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static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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cpu_outl(NULL, addr & 0xffff, value);
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}
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static uint32_t io_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret);
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#endif
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#if 0
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if (logfile)
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fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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#endif
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return ret;
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}
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CPUWriteMemoryFunc *io_write[] = {
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&io_writeb,
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&io_writew,
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&io_writel,
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};
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CPUReadMemoryFunc *io_read[] = {
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&io_readb,
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&io_readw,
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&io_readl,
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};
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void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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@ -197,7 +115,6 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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char buf[1024];
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int64_t entry = 0;
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unsigned long bios_offset;
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int io_memory;
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int ret;
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CPUState *env;
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long kernel_size;
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@ -263,8 +180,7 @@ void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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cpu_mips_irqctrl_init();
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/* Register 64 KB of ISA IO space at 0x14000000 */
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io_memory = cpu_register_io_memory(0, io_read, io_write, NULL);
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cpu_register_physical_memory(0x14000000, 0x00010000, io_memory);
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isa_mmio_init(0x14000000, 0x00010000);
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isa_mem_base = 0x10000000;
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isa_pic = pic_init(pic_irq_request, env);
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58
hw/ppc.c
58
hw/ppc.c
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@ -201,64 +201,6 @@ void cpu_ppc_reset (CPUState *env)
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}
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#endif
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static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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cpu_outb(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inb(NULL, addr & 0xffff);
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return ret;
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}
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static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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cpu_outw(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inw(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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return ret;
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}
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static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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cpu_outl(NULL, addr & 0xffff, value);
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}
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static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = cpu_inl(NULL, addr & 0xffff);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret);
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#endif
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return ret;
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}
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CPUWriteMemoryFunc *PPC_io_write[] = {
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&PPC_io_writeb,
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&PPC_io_writew,
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&PPC_io_writel,
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};
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CPUReadMemoryFunc *PPC_io_read[] = {
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&PPC_io_readb,
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&PPC_io_readw,
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&PPC_io_readl,
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};
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/*****************************************************************************/
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/* Debug port */
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void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
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SetIRQFunc *set_irq;
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void *pic;
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m48t59_t *nvram;
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int PPC_io_memory, unin_memory;
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int unin_memory;
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int linux_boot, i;
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unsigned long bios_offset, vga_bios_offset;
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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@ -417,9 +417,8 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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isa_mem_base = 0x80000000;
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/* Register 2 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory);
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isa_mmio_init(0xfe000000, 0x00200000);
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/* init basic PC hardware */
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pic = heathrow_pic_init(&heathrow_pic_mem_index);
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set_irq = heathrow_pic_set_irq;
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@ -463,8 +462,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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isa_mem_base = 0x80000000;
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/* Register 8 MB of ISA IO space */
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PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
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cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory);
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isa_mmio_init(0xf2000000, 0x00800000);
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/* UniN init */
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unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
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2
vl.h
2
vl.h
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@ -675,6 +675,8 @@ int register_ioport_write(int start, int length, int size,
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IOPortWriteFunc *func, void *opaque);
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void isa_unassign_ioport(int start, int length);
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
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/* PCI bus */
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extern target_phys_addr_t pci_mem_base;
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