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target/loongarch: Implement vadda 

This patch includes:
- VADDA.{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-13-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:38 +08:00
parent 4972565967
commit af448cb31a
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
5 changed files with 87 additions and 0 deletions
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5
target/loongarch/disas.c
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@ -934,3 +934,8 @@ INSN_LSX(vabsd_bu, vvv)
INSN_LSX(vabsd_hu, vvv)
INSN_LSX(vabsd_wu, vvv)
INSN_LSX(vabsd_du, vvv)
INSN_LSX(vadda_b, vvv)
INSN_LSX(vadda_h, vvv)
INSN_LSX(vadda_w, vvv)
INSN_LSX(vadda_d, vvv)

5
target/loongarch/helper.h
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@ -220,3 +220,8 @@ DEF_HELPER_FLAGS_4(vabsd_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vabsd_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vadda_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vadda_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vadda_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vadda_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

53
target/loongarch/insn_trans/trans_lsx.c.inc
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@ -1261,3 +1261,56 @@ TRANS(vabsd_bu, gvec_vvv, MO_8, do_vabsd_u)
TRANS(vabsd_hu, gvec_vvv, MO_16, do_vabsd_u)
TRANS(vabsd_wu, gvec_vvv, MO_32, do_vabsd_u)
TRANS(vabsd_du, gvec_vvv, MO_64, do_vabsd_u)
static void gen_vadda(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t1, t2;
t1 = tcg_temp_new_vec_matching(a);
t2 = tcg_temp_new_vec_matching(b);
tcg_gen_abs_vec(vece, t1, a);
tcg_gen_abs_vec(vece, t2, b);
tcg_gen_add_vec(vece, t, t1, t2);
}
static void do_vadda(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_abs_vec, INDEX_op_add_vec, 0
};
static const GVecGen3 op[4] = {
{
.fniv = gen_vadda,
.fno = gen_helper_vadda_b,
.opt_opc = vecop_list,
.vece = MO_8
},
{
.fniv = gen_vadda,
.fno = gen_helper_vadda_h,
.opt_opc = vecop_list,
.vece = MO_16
},
{
.fniv = gen_vadda,
.fno = gen_helper_vadda_w,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vadda,
.fno = gen_helper_vadda_d,
.opt_opc = vecop_list,
.vece = MO_64
},
};
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
}
TRANS(vadda_b, gvec_vvv, MO_8, do_vadda)
TRANS(vadda_h, gvec_vvv, MO_16, do_vadda)
TRANS(vadda_w, gvec_vvv, MO_32, do_vadda)
TRANS(vadda_d, gvec_vvv, MO_64, do_vadda)

5
target/loongarch/insns.decode
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@ -628,3 +628,8 @@ vabsd_bu 0111 00000110 00100 ..... ..... ..... @vvv
vabsd_hu 0111 00000110 00101 ..... ..... ..... @vvv
vabsd_wu 0111 00000110 00110 ..... ..... ..... @vvv
vabsd_du 0111 00000110 00111 ..... ..... ..... @vvv
vadda_b 0111 00000101 11000 ..... ..... ..... @vvv
vadda_h 0111 00000101 11001 ..... ..... ..... @vvv
vadda_w 0111 00000101 11010 ..... ..... ..... @vvv
vadda_d 0111 00000101 11011 ..... ..... ..... @vvv

19
target/loongarch/lsx_helper.c
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@ -318,3 +318,22 @@ DO_3OP(vabsd_bu, 8, UB, DO_VABSD)
DO_3OP(vabsd_hu, 16, UH, DO_VABSD)
DO_3OP(vabsd_wu, 32, UW, DO_VABSD)
DO_3OP(vabsd_du, 64, UD, DO_VABSD)
#define DO_VABS(a) ((a < 0) ? (-a) : (a))
#define DO_VADDA(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
for (i = 0; i < LSX_LEN/BIT; i++) { \
Vd->E(i) = DO_OP(Vj->E(i)) + DO_OP(Vk->E(i)); \
} \
}
DO_VADDA(vadda_b, 8, B, DO_VABS)
DO_VADDA(vadda_h, 16, H, DO_VABS)
DO_VADDA(vadda_w, 32, W, DO_VABS)
DO_VADDA(vadda_d, 64, D, DO_VABS)