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target-mips: optimize gen_movci()

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6956 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-03-29 15:44:50 +00:00
parent d94536f417
commit af58f9ca43
1 changed files with 17 additions and 15 deletions
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32
target-mips/translate.c
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@ -5693,29 +5693,31 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
{ {
int l1 = gen_new_label(); int l1;
uint32_t ccbit;
TCGCond cond; TCGCond cond;
TCGv t0 = tcg_temp_local_new(); TCGv_i32 t0;
TCGv_i32 r_tmp = tcg_temp_new_i32();
if (rd == 0) {
/* Treat as NOP. */
return;
}
if (cc)
ccbit = 1 << (24 + cc);
else
ccbit = 1 << 23;
if (tf) if (tf)
cond = TCG_COND_EQ; cond = TCG_COND_EQ;
else else
cond = TCG_COND_NE; cond = TCG_COND_NE;
gen_load_gpr(t0, rd); l1 = gen_new_label();
tcg_gen_andi_i32(r_tmp, fpu_fcr31, ccbit); t0 = tcg_temp_new_i32();
tcg_gen_brcondi_i32(cond, r_tmp, 0, l1); tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
tcg_temp_free_i32(r_tmp); tcg_gen_brcondi_i32(cond, t0, 0, l1);
gen_load_gpr(t0, rs); if (rs == 0) {
tcg_gen_movi_tl(cpu_gpr[rd], 0);
} else {
tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
}
gen_set_label(l1); gen_set_label(l1);
gen_store_gpr(t0, rd); tcg_temp_free_i32(t0);
tcg_temp_free(t0);
} }
static inline void gen_movcf_s (int fs, int fd, int cc, int tf) static inline void gen_movcf_s (int fs, int fd, int cc, int tf)