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RISC-V: Adding T-Head MemPair extension

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This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:07 +01:00 committed by Alistair Francis
parent b8a5832b87
commit af99aa72ef
5 changed files with 109 additions and 1 deletions
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2
target/riscv/cpu.c
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@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
};
@ -1101,6 +1102,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),

1
target/riscv/cpu.h
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@ -479,6 +479,7 @@ struct RISCVCPUConfig {
bool ext_xtheadcmo;
bool ext_xtheadcondmov;
bool ext_xtheadmac;
bool ext_xtheadmempair;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;

92
target/riscv/insn_trans/trans_xthead.c.inc
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@ -52,6 +52,12 @@
} \
} while (0)
#define REQUIRE_XTHEADMEMPAIR(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadmempair) { \
return false; \
} \
} while (0)
#define REQUIRE_XTHEADSYNC(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadsync) { \
return false; \
@ -382,6 +388,92 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
}
/* XTheadMemPair */
static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
int shamt)
{
if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
return false;
}
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv addr1 = tcg_temp_new();
TCGv addr2 = tcg_temp_new();
int imm = a->sh2 << shamt;
addr1 = get_address(ctx, a->rs, imm);
addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);
tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd1, t1);
gen_set_gpr(ctx, a->rd2, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(addr1);
tcg_temp_free(addr2);
return true;
}
static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a)
{
REQUIRE_XTHEADMEMPAIR(ctx);
REQUIRE_64BIT(ctx);
return gen_loadpair_tl(ctx, a, MO_TESQ, 4);
}
static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a)
{
REQUIRE_XTHEADMEMPAIR(ctx);
return gen_loadpair_tl(ctx, a, MO_TESL, 3);
}
static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
{
REQUIRE_XTHEADMEMPAIR(ctx);
return gen_loadpair_tl(ctx, a, MO_TEUL, 3);
}
static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
int shamt)
{
if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
return false;
}
TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
TCGv addr1 = tcg_temp_new();
TCGv addr2 = tcg_temp_new();
int imm = a->sh2 << shamt;
addr1 = get_address(ctx, a->rs, imm);
addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);
tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);
tcg_temp_free(addr1);
tcg_temp_free(addr2);
return true;
}
static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a)
{
REQUIRE_XTHEADMEMPAIR(ctx);
REQUIRE_64BIT(ctx);
return gen_storepair_tl(ctx, a, MO_TESQ, 4);
}
static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a)
{
REQUIRE_XTHEADMEMPAIR(ctx);
return gen_storepair_tl(ctx, a, MO_TESL, 3);
}
/* XTheadSync */
static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)

2
target/riscv/translate.c
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@ -135,7 +135,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
ctx->cfg_ptr->ext_xtheadsync;
ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \

13
target/riscv/xthead.decode
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@ -11,16 +11,21 @@
# Fields:
%rd 7:5
%rd1 7:5
%rs 15:5
%rs1 15:5
%rd2 20:5
%rs2 20:5
%sh5 20:5
%sh6 20:6
%sh2 25:2
# Argument sets
&r rd rs1 rs2 !extern
&r2 rd rs1 !extern
&shift shamt rs1 rd !extern
&th_bfext msb lsb rs1 rd
&th_pair rd1 rs rd2 sh2
# Formats
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@ -30,6 +35,7 @@
@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
# XTheadBa
# Instead of defining a new encoding, we simply use the decoder to
@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r
th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r
th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r
# XTheadMemPair
th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair
th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair
th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair
th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair
th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair
# XTheadSync
th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s
th_sync 0000000 11000 00000 000 00000 0001011