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i386: Update stepping of Cascadelake-Server

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Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20181227024304.12182-2-tao3.xu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Tao Xu 2018-12-27 10:43:03 +08:00 committed by Eduardo Habkost
parent 5f39a91dbd
commit b0a1980384
2 changed files with 2 additions and 1 deletions
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1
hw/i386/pc.c
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@ -122,6 +122,7 @@ GlobalProperty pc_compat_3_1[] = {
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
};
const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);

2
target/i386/cpu.c
View File

@ -2503,7 +2503,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
.stepping = 5,
.stepping = 6,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |