ppc/pnv: Remove PnvOCC::psi link
Use an anonymous output GPIO line to connect the OCC device with the PSIHB device and raise the appropriate PSI IRQ line depending on the processor model. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-4-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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12
hw/ppc/pnv.c
12
hw/ppc/pnv.c
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@ -1253,12 +1253,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
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}
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}
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/* Create the simplified OCC model */
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/* Create the simplified OCC model */
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object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
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&error_abort);
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if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
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if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
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return;
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return;
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}
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}
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pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
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pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
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qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
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qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
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/* OCC SRAM model */
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
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memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
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@ -1528,12 +1528,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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(uint64_t) PNV9_LPCM_BASE(chip));
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(uint64_t) PNV9_LPCM_BASE(chip));
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/* Create the simplified OCC model */
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/* Create the simplified OCC model */
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object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
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&error_abort);
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if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
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if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
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return;
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return;
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}
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}
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pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
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pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
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qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
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DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
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/* OCC SRAM model */
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
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memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
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@ -1731,13 +1731,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
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(uint64_t) PNV10_LPCM_BASE(chip));
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(uint64_t) PNV10_LPCM_BASE(chip));
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/* Create the simplified OCC model */
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/* Create the simplified OCC model */
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object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
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&error_abort);
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if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
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if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
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return;
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return;
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}
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}
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
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&chip10->occ.xscom_regs);
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&chip10->occ.xscom_regs);
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qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
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DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
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/* OCC SRAM model */
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(),
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memory_region_add_subregion(get_system_memory(),
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@ -21,6 +21,7 @@
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#include "qapi/error.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_xscom.h"
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@ -51,13 +52,12 @@
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static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
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static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
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{
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{
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bool irq_state;
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bool irq_state;
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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val &= 0xffff000000000000ull;
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val &= 0xffff000000000000ull;
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occ->occmisc = val;
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occ->occmisc = val;
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irq_state = !!(val >> 63);
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irq_state = !!(val >> 63);
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pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
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qemu_set_irq(occ->psi_irq, irq_state);
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}
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}
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static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
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static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
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@ -168,7 +168,6 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
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poc->xscom_size = PNV_XSCOM_OCC_SIZE;
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poc->xscom_size = PNV_XSCOM_OCC_SIZE;
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poc->xscom_ops = &pnv_occ_power8_xscom_ops;
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poc->xscom_ops = &pnv_occ_power8_xscom_ops;
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poc->psi_irq = PSIHB_IRQ_OCC;
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}
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}
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static const TypeInfo pnv_occ_power8_type_info = {
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static const TypeInfo pnv_occ_power8_type_info = {
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@ -241,7 +240,6 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
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dc->desc = "PowerNV OCC Controller (POWER9)";
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dc->desc = "PowerNV OCC Controller (POWER9)";
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poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
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poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
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poc->xscom_ops = &pnv_occ_power9_xscom_ops;
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poc->xscom_ops = &pnv_occ_power9_xscom_ops;
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poc->psi_irq = PSIHB9_IRQ_OCC;
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}
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}
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static const TypeInfo pnv_occ_power9_type_info = {
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static const TypeInfo pnv_occ_power9_type_info = {
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@ -269,8 +267,6 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
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PnvOCC *occ = PNV_OCC(dev);
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PnvOCC *occ = PNV_OCC(dev);
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
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assert(occ->psi);
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occ->occmisc = 0;
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occ->occmisc = 0;
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/* XScom region for OCC registers */
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/* XScom region for OCC registers */
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@ -281,12 +277,9 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
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memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
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memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
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occ, "occ-common-area",
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occ, "occ-common-area",
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PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
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PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
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}
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static Property pnv_occ_properties[] = {
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qdev_init_gpio_out(DEVICE(dev), &occ->psi_irq, 1);
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DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
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}
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_occ_class_init(ObjectClass *klass, void *data)
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static void pnv_occ_class_init(ObjectClass *klass, void *data)
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{
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{
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@ -294,7 +287,6 @@ static void pnv_occ_class_init(ObjectClass *klass, void *data)
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dc->realize = pnv_occ_realize;
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dc->realize = pnv_occ_realize;
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dc->desc = "PowerNV OCC Controller";
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dc->desc = "PowerNV OCC Controller";
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device_class_set_props(dc, pnv_occ_properties);
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dc->user_creatable = false;
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dc->user_creatable = false;
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}
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}
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@ -1,7 +1,7 @@
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/*
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/*
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* QEMU PowerPC PowerNV Emulation of a few OCC related registers
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* QEMU PowerPC PowerNV Emulation of a few OCC related registers
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*
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*
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* Copyright (c) 2015-2017, IBM Corporation.
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* Copyright (c) 2015-2022, IBM Corporation.
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*
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*
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* This library is free software; you can redistribute it and/or
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* modify it under the terms of the GNU Lesser General Public
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@ -20,7 +20,6 @@
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#ifndef PPC_PNV_OCC_H
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#ifndef PPC_PNV_OCC_H
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#define PPC_PNV_OCC_H
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#define PPC_PNV_OCC_H
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#include "hw/ppc/pnv_psi.h"
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#include "qom/object.h"
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#include "qom/object.h"
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#define TYPE_PNV_OCC "pnv-occ"
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#define TYPE_PNV_OCC "pnv-occ"
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@ -44,19 +43,17 @@ struct PnvOCC {
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/* OCC Misc interrupt */
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/* OCC Misc interrupt */
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uint64_t occmisc;
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uint64_t occmisc;
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PnvPsi *psi;
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qemu_irq psi_irq;
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MemoryRegion xscom_regs;
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MemoryRegion xscom_regs;
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MemoryRegion sram_regs;
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MemoryRegion sram_regs;
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};
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};
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struct PnvOCCClass {
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struct PnvOCCClass {
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DeviceClass parent_class;
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DeviceClass parent_class;
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int xscom_size;
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int xscom_size;
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const MemoryRegionOps *xscom_ops;
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const MemoryRegionOps *xscom_ops;
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int psi_irq;
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};
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};
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#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
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#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
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