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target/arm: Use field names for manipulating EL2 and EL3 modes

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Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-06 13:02:28 -05:00 committed by Peter Maydell
parent ef696cfbae
commit b13c91c04b
1 changed files with 13 additions and 9 deletions
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22
target/arm/cpu.c
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@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
*/
unset_feature(env, ARM_FEATURE_EL3);
/* Disable the security extension feature bits in the processor feature
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
/*
* Disable the security extension feature bits in the processor
* feature registers as well.
*/
cpu->isar.id_pfr1 &= ~0xf0;
cpu->isar.id_aa64pfr0 &= ~0xf000;
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
ID_AA64PFR0, EL3, 0);
}
if (!cpu->has_el2) {
@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
/* Disable the hypervisor feature bits in the processor feature
* registers if we don't have EL2. These are id_pfr1[15:12] and
* id_aa64pfr0_el1[11:8].
/*
* Disable the hypervisor feature bits in the processor feature
* registers if we don't have EL2.
*/
cpu->isar.id_aa64pfr0 &= ~0xf00;
cpu->isar.id_pfr1 &= ~0xf000;
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
ID_AA64PFR0, EL2, 0);
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
ID_PFR1, VIRTUALIZATION, 0);
}
#ifndef CONFIG_USER_ONLY