OpenE2K/qemu-e2k
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Always make all PowerPC exception definitions visible.

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Always make the hypervisor timers available.
Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases
that cannot be properly handled with the current PowerPC CPU definition.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-11-17 01:37:44 +00:00
parent 5a6932d51d
commit b172c56a6d
7 changed files with 69 additions and 76 deletions
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6
darwin-user/main.c
View File

@ -386,7 +386,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(env, "Reset interrupt while in user mode. "
"Aborting\n");
break;
#if defined(TARGET_PPC64) /* PowerPC 64 */
case POWERPC_EXCP_DSEG: /* Data segment exception */
cpu_abort(env, "Data segment exception while in user mode. "
"Aborting\n");
@ -395,19 +394,15 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(env, "Instruction segment exception "
"while in user mode. Aborting\n");
break;
#endif /* defined(TARGET_PPC64) */
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
cpu_abort(env, "Hypervisor decrementer interrupt "
"while in user mode. Aborting\n");
break;
#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_TRACE: /* Trace exception */
/* Nothing to do:
* we use this exception to emulate step-by-step execution mode.
*/
break;
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
cpu_abort(env, "Hypervisor data storage exception "
"while in user mode. Aborting\n");
@ -424,7 +419,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(env, "Hypervisor instruction segment exception "
"while in user mode. Aborting\n");
break;
#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
EXCP_DUMP(env, "No Altivec instructions allowed\n");
info.si_signo = SIGILL;

24
hw/ppc.c
View File

@ -428,13 +428,11 @@ struct ppc_tb_t {
uint64_t decr_next; /* Tick for next decr interrupt */
uint32_t decr_freq; /* decrementer frequency */
struct QEMUTimer *decr_timer;
#if defined(TARGET_PPC64H)
/* Hypervisor decrementer management */
uint64_t hdecr_next; /* Tick for next hdecr interrupt */
struct QEMUTimer *hdecr_timer;
uint64_t purr_load;
uint64_t purr_start;
#endif
void *opaque;
};
@ -643,7 +641,6 @@ uint32_t cpu_ppc_load_decr (CPUState *env)
return _cpu_ppc_load_decr(env, &tb_env->decr_next);
}
#if defined(TARGET_PPC64H)
uint32_t cpu_ppc_load_hdecr (CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
@ -660,7 +657,6 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
}
#endif /* defined(TARGET_PPC64H) */
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
@ -736,14 +732,15 @@ static void cpu_ppc_decr_cb (void *opaque)
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
#if defined(TARGET_PPC64H)
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
__cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
&cpu_ppc_hdecr_excp, hdecr, value, is_excp);
if (tb_env->hdecr_timer != NULL) {
__cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
&cpu_ppc_hdecr_excp, hdecr, value, is_excp);
}
}
void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
@ -763,7 +760,6 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value)
tb_env->purr_load = value;
tb_env->purr_start = qemu_get_clock(vm_clock);
}
#endif /* defined(TARGET_PPC64H) */
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
{
@ -777,10 +773,8 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
* it's not ready to handle it...
*/
_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
#if defined(TARGET_PPC64H)
_cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
cpu_ppc_store_purr(env, 0x0000000000000000ULL);
#endif /* defined(TARGET_PPC64H) */
}
/* Set up (once) timebase frequency (in Hz) */
@ -794,9 +788,13 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
env->tb_env = tb_env;
/* Create new timer */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
#if defined(TARGET_PPC64H)
tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
#endif /* defined(TARGET_PPC64H) */
if (0) {
/* XXX: find a suitable condition to enable the hypervisor decrementer
*/
tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
} else {
tb_env->hdecr_timer = NULL;
}
cpu_ppc_set_tb_clk(env, freq);
return &cpu_ppc_set_tb_clk;

6
linux-user/main.c
View File

@ -1047,7 +1047,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(env, "Reset interrupt while in user mode. "
"Aborting\n");
break;
#if defined(TARGET_PPC64) && !defined(TARGET_ABI32) /* PowerPC 64 */
case POWERPC_EXCP_DSEG: /* Data segment exception */
cpu_abort(env, "Data segment exception while in user mode. "
"Aborting\n");
@ -1056,20 +1055,16 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(env, "Instruction segment exception "
"while in user mode. Aborting\n");
break;
#endif /* defined(TARGET_PPC64) && !defined(TARGET_ABI32) */
#if defined(TARGET_PPC64H) && !defined(TARGET_ABI32)
/* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
cpu_abort(env, "Hypervisor decrementer interrupt "
"while in user mode. Aborting\n");
break;
#endif /* defined(TARGET_PPC64H) && !defined(TARGET_ABI32) */
case POWERPC_EXCP_TRACE: /* Trace exception */
/* Nothing to do:
* we use this exception to emulate step-by-step execution mode.
*/
break;
#if defined(TARGET_PPC64H) && !defined(TARGET_ABI32)
/* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
cpu_abort(env, "Hypervisor data storage exception "
@ -1087,7 +1082,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(env, "Hypervisor instruction segment exception "
"while in user mode. Aborting\n");
break;
#endif /* defined(TARGET_PPC64H) && !defined(TARGET_ABI32) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
EXCP_DUMP(env, "No Altivec instructions allowed\n");
info.si_signo = TARGET_SIGILL;

8
target-ppc/cpu.h
View File

@ -180,20 +180,14 @@ enum {
/* Vectors 38 to 63 are reserved */
/* Exceptions defined in the PowerPC server specification */
POWERPC_EXCP_RESET = 64, /* System reset exception */
#if defined(TARGET_PPC64) /* PowerPC 64 */
POWERPC_EXCP_DSEG = 65, /* Data segment exception */
POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
#endif /* defined(TARGET_PPC64) */
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
#endif /* defined(TARGET_PPC64H) */
POWERPC_EXCP_TRACE = 68, /* Trace exception */
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
#endif /* defined(TARGET_PPC64H) */
POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
/* 40x specific exceptions */
POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
@ -736,12 +730,10 @@ void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
#if defined(TARGET_PPC64H)
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
#endif
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)

92
target-ppc/helper.c
View File

@ -2134,13 +2134,21 @@ static always_inline void powerpc_excp (CPUState *env,
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
#if defined(TARGET_PPC64H)
int lpes0, lpes1, lev;
lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
int lpes0, lpes1;
#if defined(TARGET_PPC64)
int lev;
#endif
if (0) {
/* XXX: find a suitable condition to enable the hypervisor mode */
lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
} else {
/* Those values ensure we won't enter the hypervisor mode */
lpes0 = 0;
lpes1 = 1;
}
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
env->nip, excp, env->error_code);
@ -2190,8 +2198,11 @@ static always_inline void powerpc_excp (CPUState *env,
}
new_msr &= ~((target_ulong)1 << MSR_RI);
new_msr &= ~((target_ulong)1 << MSR_ME);
#if defined(TARGET_PPC64H)
new_msr |= (target_ulong)1 << MSR_HV;
#if defined(TARGET_PPC64)
if (0) {
/* XXX: find a suitable condition to enable the hypervisor mode */
new_msr |= (target_ulong)1 << MSR_HV;
}
#endif
/* XXX: should also have something loaded in DAR / DSISR */
switch (excp_model) {
@ -2217,7 +2228,7 @@ static always_inline void powerpc_excp (CPUState *env,
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2230,7 +2241,7 @@ static always_inline void powerpc_excp (CPUState *env,
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2238,14 +2249,14 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_EXTERNAL: /* External input */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes0 == 1)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2267,7 +2278,7 @@ static always_inline void powerpc_excp (CPUState *env,
return;
}
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2284,7 +2295,7 @@ static always_inline void powerpc_excp (CPUState *env,
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2292,7 +2303,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_PRIV:
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2300,7 +2311,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_TRAP:
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2315,7 +2326,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_current;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2336,7 +2347,7 @@ static always_inline void powerpc_excp (CPUState *env,
dump_syscall(env);
}
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
lev = env->error_code;
if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
new_msr |= (target_ulong)1 << MSR_HV;
@ -2347,7 +2358,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_current;
case POWERPC_EXCP_DECR: /* Decrementer exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2434,65 +2445,69 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_RESET: /* System reset exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
#if defined(TARGET_PPC64)
case POWERPC_EXCP_DSEG: /* Data segment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
#endif /* defined(TARGET_PPC64) */
#if defined(TARGET_PPC64H)
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
goto store_next;
#endif
goto store_next;
case POWERPC_EXCP_TRACE: /* Trace exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
#if defined(TARGET_PPC64H)
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2519,7 +2534,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
#if defined(TARGET_PPC64H) /* XXX: check this */
#if defined(TARGET_PPC64) /* XXX: check this */
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2540,7 +2555,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
#if defined(TARGET_PPC64H) /* XXX: check this */
#if defined(TARGET_PPC64) /* XXX: check this */
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2561,7 +2576,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
#if defined(TARGET_PPC64H) /* XXX: check this */
#if defined(TARGET_PPC64) /* XXX: check this */
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2663,7 +2678,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
new_msr &= ~((target_ulong)1 << MSR_RI);
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@ -2769,7 +2784,7 @@ void do_interrupt (CPUState *env)
void ppc_hw_interrupt (CPUPPCState *env)
{
#if defined(TARGET_PPC64H)
#if defined(TARGET_PPC64)
int hdice;
#endif
@ -2800,8 +2815,13 @@ void ppc_hw_interrupt (CPUPPCState *env)
return;
}
#endif
#if defined(TARGET_PPC64H)
hdice = env->spr[SPR_LPCR] & 1;
#if defined(TARGET_PPC64)
if (0) {
/* XXX: find a suitable condition to enable the hypervisor mode */
hdice = env->spr[SPR_LPCR] & 1;
} else {
hdice = 0;
}
if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
/* Hypervisor decrementer exception */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {

7
target-ppc/helper_regs.h
View File

@ -60,7 +60,7 @@ static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
{
#if defined (TARGET_PPC64H)
#if defined (TARGET_PPC64)
/* Precompute MMU index */
if (msr_pr == 0 && msr_hv != 0)
env->mmu_idx = 2;
@ -78,10 +78,7 @@ static always_inline void hreg_compute_hflags (CPUPPCState *env)
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
(1 << MSR_LE);
#if defined (TARGET_PPC64)
hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF);
#if defined (TARGET_PPC64H)
hflags_mask |= 1ULL << MSR_HV;
#endif
hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | (1ULL << MSR_HV);
#endif
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;

2
target-ppc/translate_init.c
View File

@ -2609,9 +2609,7 @@ static void init_excp_970 (CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
#endif
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;