target-hppa: Implement basic arithmetic
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
129e9cc3a1
commit
b2167459ae
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@ -1,3 +1,5 @@
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DEF_HELPER_2(excp, noreturn, env, int)
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DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl)
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DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl)
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DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env)
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@ -31,6 +31,29 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp)
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cpu_loop_exit(cs);
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}
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static void QEMU_NORETURN dynexcp(CPUHPPAState *env, int excp, uintptr_t ra)
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{
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HPPACPU *cpu = hppa_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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cs->exception_index = excp;
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cpu_loop_exit_restore(cs, ra);
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}
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void HELPER(tsv)(CPUHPPAState *env, target_ulong cond)
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{
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if (unlikely((target_long)cond < 0)) {
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dynexcp(env, EXCP_SIGFPE, GETPC());
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}
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}
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void HELPER(tcond)(CPUHPPAState *env, target_ulong cond)
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{
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if (unlikely(cond)) {
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dynexcp(env, EXCP_SIGFPE, GETPC());
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}
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}
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void HELPER(loaded_fr0)(CPUHPPAState *env)
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{
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uint32_t shadow = env->fr[0] >> 32;
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@ -83,6 +83,9 @@ typedef struct DisasInsn {
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uint32_t insn, mask;
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ExitStatus (*trans)(DisasContext *ctx, uint32_t insn,
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const struct DisasInsn *f);
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union {
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void (*f_ttt)(TCGv, TCGv, TCGv);
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};
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} DisasInsn;
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/* global register indexes */
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@ -443,6 +446,870 @@ static void gen_goto_tb(DisasContext *ctx, int which,
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}
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}
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/* PA has a habit of taking the LSB of a field and using that as the sign,
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with the rest of the field becoming the least significant bits. */
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static target_long low_sextract(uint32_t val, int pos, int len)
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{
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target_ulong x = -(target_ulong)extract32(val, pos, 1);
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x = (x << (len - 1)) | extract32(val, pos + 1, len - 1);
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return x;
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}
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static target_long assemble_16(uint32_t insn)
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{
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/* Take the name from PA2.0, which produces a 16-bit number
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only with wide mode; otherwise a 14-bit number. Since we don't
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implement wide mode, this is always the 14-bit number. */
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return low_sextract(insn, 0, 14);
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}
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static target_long assemble_21(uint32_t insn)
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{
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target_ulong x = -(target_ulong)(insn & 1);
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x = (x << 11) | extract32(insn, 1, 11);
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x = (x << 2) | extract32(insn, 14, 2);
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x = (x << 5) | extract32(insn, 16, 5);
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x = (x << 2) | extract32(insn, 12, 2);
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return x << 11;
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}
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/* The parisc documentation describes only the general interpretation of
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the conditions, without describing their exact implementation. The
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interpretations do not stand up well when considering ADD,C and SUB,B.
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However, considering the Addition, Subtraction and Logical conditions
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as a whole it would appear that these relations are similar to what
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a traditional NZCV set of flags would produce. */
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static DisasCond do_cond(unsigned cf, TCGv res, TCGv cb_msb, TCGv sv)
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{
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DisasCond cond;
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TCGv tmp;
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switch (cf >> 1) {
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case 0: /* Never / TR */
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cond = cond_make_f();
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break;
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case 1: /* = / <> (Z / !Z) */
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cond = cond_make_0(TCG_COND_EQ, res);
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break;
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case 2: /* < / >= (N / !N) */
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cond = cond_make_0(TCG_COND_LT, res);
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break;
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case 3: /* <= / > (N | Z / !N & !Z) */
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cond = cond_make_0(TCG_COND_LE, res);
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break;
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case 4: /* NUV / UV (!C / C) */
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cond = cond_make_0(TCG_COND_EQ, cb_msb);
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break;
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case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
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tmp = tcg_temp_new();
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tcg_gen_neg_tl(tmp, cb_msb);
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tcg_gen_and_tl(tmp, tmp, res);
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cond = cond_make_0(TCG_COND_EQ, tmp);
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tcg_temp_free(tmp);
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break;
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case 6: /* SV / NSV (V / !V) */
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cond = cond_make_0(TCG_COND_LT, sv);
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break;
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case 7: /* OD / EV */
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tmp = tcg_temp_new();
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tcg_gen_andi_tl(tmp, res, 1);
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cond = cond_make_0(TCG_COND_NE, tmp);
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tcg_temp_free(tmp);
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break;
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default:
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g_assert_not_reached();
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}
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if (cf & 1) {
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cond.c = tcg_invert_cond(cond.c);
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}
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return cond;
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}
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/* Similar, but for the special case of subtraction without borrow, we
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can use the inputs directly. This can allow other computation to be
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deleted as unused. */
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static DisasCond do_sub_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2, TCGv sv)
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{
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DisasCond cond;
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switch (cf >> 1) {
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case 1: /* = / <> */
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cond = cond_make(TCG_COND_EQ, in1, in2);
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break;
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case 2: /* < / >= */
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cond = cond_make(TCG_COND_LT, in1, in2);
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break;
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case 3: /* <= / > */
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cond = cond_make(TCG_COND_LE, in1, in2);
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break;
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case 4: /* << / >>= */
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cond = cond_make(TCG_COND_LTU, in1, in2);
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break;
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case 5: /* <<= / >> */
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cond = cond_make(TCG_COND_LEU, in1, in2);
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break;
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default:
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return do_cond(cf, res, sv, sv);
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}
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if (cf & 1) {
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cond.c = tcg_invert_cond(cond.c);
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}
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return cond;
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}
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/* Similar, but for logicals, where the carry and overflow bits are not
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computed, and use of them is undefined. */
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static DisasCond do_log_cond(unsigned cf, TCGv res)
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{
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switch (cf >> 1) {
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case 4: case 5: case 6:
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cf &= 1;
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break;
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}
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return do_cond(cf, res, res, res);
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}
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/* Similar, but for unit conditions. */
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static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2)
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{
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DisasCond cond;
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TCGv tmp, cb;
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TCGV_UNUSED(cb);
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if (cf & 8) {
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/* Since we want to test lots of carry-out bits all at once, do not
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* do our normal thing and compute carry-in of bit B+1 since that
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* leaves us with carry bits spread across two words.
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*/
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cb = tcg_temp_new();
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tmp = tcg_temp_new();
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tcg_gen_or_tl(cb, in1, in2);
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tcg_gen_and_tl(tmp, in1, in2);
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tcg_gen_andc_tl(cb, cb, res);
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tcg_gen_or_tl(cb, cb, tmp);
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tcg_temp_free(tmp);
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}
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switch (cf >> 1) {
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case 0: /* never / TR */
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case 1: /* undefined */
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case 5: /* undefined */
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cond = cond_make_f();
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break;
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case 2: /* SBZ / NBZ */
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/* See hasless(v,1) from
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* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
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*/
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tmp = tcg_temp_new();
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tcg_gen_subi_tl(tmp, res, 0x01010101u);
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tcg_gen_andc_tl(tmp, tmp, res);
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tcg_gen_andi_tl(tmp, tmp, 0x80808080u);
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cond = cond_make_0(TCG_COND_NE, tmp);
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tcg_temp_free(tmp);
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break;
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case 3: /* SHZ / NHZ */
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tmp = tcg_temp_new();
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tcg_gen_subi_tl(tmp, res, 0x00010001u);
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tcg_gen_andc_tl(tmp, tmp, res);
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tcg_gen_andi_tl(tmp, tmp, 0x80008000u);
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cond = cond_make_0(TCG_COND_NE, tmp);
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tcg_temp_free(tmp);
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break;
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case 4: /* SDC / NDC */
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tcg_gen_andi_tl(cb, cb, 0x88888888u);
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cond = cond_make_0(TCG_COND_NE, cb);
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break;
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case 6: /* SBC / NBC */
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tcg_gen_andi_tl(cb, cb, 0x80808080u);
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cond = cond_make_0(TCG_COND_NE, cb);
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break;
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case 7: /* SHC / NHC */
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tcg_gen_andi_tl(cb, cb, 0x80008000u);
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cond = cond_make_0(TCG_COND_NE, cb);
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break;
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default:
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g_assert_not_reached();
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}
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if (cf & 8) {
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tcg_temp_free(cb);
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}
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if (cf & 1) {
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cond.c = tcg_invert_cond(cond.c);
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}
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return cond;
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}
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/* Compute signed overflow for addition. */
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static TCGv do_add_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2)
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{
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TCGv sv = get_temp(ctx);
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TCGv tmp = tcg_temp_new();
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tcg_gen_xor_tl(sv, res, in1);
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tcg_gen_xor_tl(tmp, in1, in2);
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tcg_gen_andc_tl(sv, sv, tmp);
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tcg_temp_free(tmp);
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return sv;
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}
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/* Compute signed overflow for subtraction. */
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static TCGv do_sub_sv(DisasContext *ctx, TCGv res, TCGv in1, TCGv in2)
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{
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TCGv sv = get_temp(ctx);
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TCGv tmp = tcg_temp_new();
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tcg_gen_xor_tl(sv, res, in1);
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tcg_gen_xor_tl(tmp, in1, in2);
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tcg_gen_and_tl(sv, sv, tmp);
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tcg_temp_free(tmp);
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return sv;
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}
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static ExitStatus do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2,
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unsigned shift, bool is_l, bool is_tsv, bool is_tc,
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bool is_c, unsigned cf)
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{
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TCGv dest, cb, cb_msb, sv, tmp;
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unsigned c = cf >> 1;
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DisasCond cond;
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dest = tcg_temp_new();
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TCGV_UNUSED(cb);
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TCGV_UNUSED(cb_msb);
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if (shift) {
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tmp = get_temp(ctx);
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tcg_gen_shli_tl(tmp, in1, shift);
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in1 = tmp;
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}
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if (!is_l || c == 4 || c == 5) {
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TCGv zero = tcg_const_tl(0);
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cb_msb = get_temp(ctx);
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tcg_gen_add2_tl(dest, cb_msb, in1, zero, in2, zero);
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if (is_c) {
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tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero);
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}
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tcg_temp_free(zero);
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if (!is_l) {
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cb = get_temp(ctx);
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tcg_gen_xor_tl(cb, in1, in2);
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tcg_gen_xor_tl(cb, cb, dest);
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}
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} else {
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tcg_gen_add_tl(dest, in1, in2);
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if (is_c) {
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tcg_gen_add_tl(dest, dest, cpu_psw_cb_msb);
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}
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}
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/* Compute signed overflow if required. */
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TCGV_UNUSED(sv);
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if (is_tsv || c == 6) {
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sv = do_add_sv(ctx, dest, in1, in2);
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if (is_tsv) {
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/* ??? Need to include overflow from shift. */
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gen_helper_tsv(cpu_env, sv);
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}
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}
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/* Emit any conditional trap before any writeback. */
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cond = do_cond(cf, dest, cb_msb, sv);
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if (is_tc) {
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cond_prep(&cond);
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tmp = tcg_temp_new();
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tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(cpu_env, tmp);
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tcg_temp_free(tmp);
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}
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/* Write back the result. */
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if (!is_l) {
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save_or_nullify(ctx, cpu_psw_cb, cb);
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save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb);
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}
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save_gpr(ctx, rt, dest);
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tcg_temp_free(dest);
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/* Install the new nullification. */
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cond_free(&ctx->null_cond);
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ctx->null_cond = cond;
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return NO_EXIT;
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}
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static ExitStatus do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2,
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bool is_tsv, bool is_b, bool is_tc, unsigned cf)
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{
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TCGv dest, sv, cb, cb_msb, zero, tmp;
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unsigned c = cf >> 1;
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DisasCond cond;
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dest = tcg_temp_new();
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cb = tcg_temp_new();
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cb_msb = tcg_temp_new();
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zero = tcg_const_tl(0);
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if (is_b) {
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/* DEST,C = IN1 + ~IN2 + C. */
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tcg_gen_not_tl(cb, in2);
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tcg_gen_add2_tl(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero);
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tcg_gen_add2_tl(dest, cb_msb, dest, cb_msb, cb, zero);
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tcg_gen_xor_tl(cb, cb, in1);
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tcg_gen_xor_tl(cb, cb, dest);
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} else {
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/* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
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operations by seeding the high word with 1 and subtracting. */
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tcg_gen_movi_tl(cb_msb, 1);
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tcg_gen_sub2_tl(dest, cb_msb, in1, cb_msb, in2, zero);
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tcg_gen_eqv_tl(cb, in1, in2);
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tcg_gen_xor_tl(cb, cb, dest);
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}
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tcg_temp_free(zero);
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/* Compute signed overflow if required. */
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TCGV_UNUSED(sv);
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if (is_tsv || c == 6) {
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sv = do_sub_sv(ctx, dest, in1, in2);
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if (is_tsv) {
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gen_helper_tsv(cpu_env, sv);
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}
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}
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/* Compute the condition. We cannot use the special case for borrow. */
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if (!is_b) {
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cond = do_sub_cond(cf, dest, in1, in2, sv);
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} else {
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cond = do_cond(cf, dest, cb_msb, sv);
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}
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/* Emit any conditional trap before any writeback. */
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if (is_tc) {
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cond_prep(&cond);
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tmp = tcg_temp_new();
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tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1);
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gen_helper_tcond(cpu_env, tmp);
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tcg_temp_free(tmp);
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}
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/* Write back the result. */
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save_or_nullify(ctx, cpu_psw_cb, cb);
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save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb);
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save_gpr(ctx, rt, dest);
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tcg_temp_free(dest);
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/* Install the new nullification. */
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cond_free(&ctx->null_cond);
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ctx->null_cond = cond;
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return NO_EXIT;
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}
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static ExitStatus do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1,
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TCGv in2, unsigned cf)
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{
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TCGv dest, sv;
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DisasCond cond;
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dest = tcg_temp_new();
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tcg_gen_sub_tl(dest, in1, in2);
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/* Compute signed overflow if required. */
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TCGV_UNUSED(sv);
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if ((cf >> 1) == 6) {
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sv = do_sub_sv(ctx, dest, in1, in2);
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}
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/* Form the condition for the compare. */
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cond = do_sub_cond(cf, dest, in1, in2, sv);
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/* Clear. */
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tcg_gen_movi_tl(dest, 0);
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save_gpr(ctx, rt, dest);
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tcg_temp_free(dest);
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/* Install the new nullification. */
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cond_free(&ctx->null_cond);
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ctx->null_cond = cond;
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2,
|
||||
unsigned cf, void (*fn)(TCGv, TCGv, TCGv))
|
||||
{
|
||||
TCGv dest = dest_gpr(ctx, rt);
|
||||
|
||||
/* Perform the operation, and writeback. */
|
||||
fn(dest, in1, in2);
|
||||
save_gpr(ctx, rt, dest);
|
||||
|
||||
/* Install the new nullification. */
|
||||
cond_free(&ctx->null_cond);
|
||||
if (cf) {
|
||||
ctx->null_cond = do_log_cond(cf, dest);
|
||||
}
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus do_unit(DisasContext *ctx, unsigned rt, TCGv in1,
|
||||
TCGv in2, unsigned cf, bool is_tc,
|
||||
void (*fn)(TCGv, TCGv, TCGv))
|
||||
{
|
||||
TCGv dest;
|
||||
DisasCond cond;
|
||||
|
||||
if (cf == 0) {
|
||||
dest = dest_gpr(ctx, rt);
|
||||
fn(dest, in1, in2);
|
||||
save_gpr(ctx, rt, dest);
|
||||
cond_free(&ctx->null_cond);
|
||||
} else {
|
||||
dest = tcg_temp_new();
|
||||
fn(dest, in1, in2);
|
||||
|
||||
cond = do_unit_cond(cf, dest, in1, in2);
|
||||
|
||||
if (is_tc) {
|
||||
TCGv tmp = tcg_temp_new();
|
||||
cond_prep(&cond);
|
||||
tcg_gen_setcond_tl(cond.c, tmp, cond.a0, cond.a1);
|
||||
gen_helper_tcond(cpu_env, tmp);
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
save_gpr(ctx, rt, dest);
|
||||
|
||||
cond_free(&ctx->null_cond);
|
||||
ctx->null_cond = cond;
|
||||
}
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus trans_nop(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
cond_free(&ctx->null_cond);
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus trans_add(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned ext = extract32(insn, 8, 4);
|
||||
unsigned shift = extract32(insn, 6, 2);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tcg_r1, tcg_r2;
|
||||
bool is_c = false;
|
||||
bool is_l = false;
|
||||
bool is_tc = false;
|
||||
bool is_tsv = false;
|
||||
ExitStatus ret;
|
||||
|
||||
switch (ext) {
|
||||
case 0x6: /* ADD, SHLADD */
|
||||
break;
|
||||
case 0xa: /* ADD,L, SHLADD,L */
|
||||
is_l = true;
|
||||
break;
|
||||
case 0xe: /* ADD,TSV, SHLADD,TSV (1) */
|
||||
is_tsv = true;
|
||||
break;
|
||||
case 0x7: /* ADD,C */
|
||||
is_c = true;
|
||||
break;
|
||||
case 0xf: /* ADD,C,TSV */
|
||||
is_c = is_tsv = true;
|
||||
break;
|
||||
default:
|
||||
return gen_illegal(ctx);
|
||||
}
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, r1);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_add(ctx, rt, tcg_r1, tcg_r2, shift, is_l, is_tsv, is_tc, is_c, cf);
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_sub(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned ext = extract32(insn, 6, 6);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tcg_r1, tcg_r2;
|
||||
bool is_b = false;
|
||||
bool is_tc = false;
|
||||
bool is_tsv = false;
|
||||
ExitStatus ret;
|
||||
|
||||
switch (ext) {
|
||||
case 0x10: /* SUB */
|
||||
break;
|
||||
case 0x30: /* SUB,TSV */
|
||||
is_tsv = true;
|
||||
break;
|
||||
case 0x14: /* SUB,B */
|
||||
is_b = true;
|
||||
break;
|
||||
case 0x34: /* SUB,B,TSV */
|
||||
is_b = is_tsv = true;
|
||||
break;
|
||||
case 0x13: /* SUB,TC */
|
||||
is_tc = true;
|
||||
break;
|
||||
case 0x33: /* SUB,TSV,TC */
|
||||
is_tc = is_tsv = true;
|
||||
break;
|
||||
default:
|
||||
return gen_illegal(ctx);
|
||||
}
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, r1);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_sub(ctx, rt, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, cf);
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_log(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tcg_r1, tcg_r2;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, r1);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_log(ctx, rt, tcg_r1, tcg_r2, cf, di->f_ttt);
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
/* OR r,0,t -> COPY (according to gas) */
|
||||
static ExitStatus trans_copy(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
|
||||
if (r1 == 0) {
|
||||
TCGv dest = dest_gpr(ctx, rt);
|
||||
tcg_gen_movi_tl(dest, 0);
|
||||
save_gpr(ctx, rt, dest);
|
||||
} else {
|
||||
save_gpr(ctx, rt, cpu_gr[r1]);
|
||||
}
|
||||
cond_free(&ctx->null_cond);
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus trans_cmpclr(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tcg_r1, tcg_r2;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, r1);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_cmpclr(ctx, rt, tcg_r1, tcg_r2, cf);
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_uxor(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tcg_r1, tcg_r2;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, r1);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_tl);
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_uaddcm(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned is_tc = extract32(insn, 6, 1);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tcg_r1, tcg_r2, tmp;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
tcg_r1 = load_gpr(ctx, r1);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
tmp = get_temp(ctx);
|
||||
tcg_gen_not_tl(tmp, tcg_r2);
|
||||
ret = do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_tl);
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_dcor(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned is_i = extract32(insn, 6, 1);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv tmp;
|
||||
ExitStatus ret;
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
tmp = get_temp(ctx);
|
||||
tcg_gen_shri_tl(tmp, cpu_psw_cb, 3);
|
||||
if (!is_i) {
|
||||
tcg_gen_not_tl(tmp, tmp);
|
||||
}
|
||||
tcg_gen_andi_tl(tmp, tmp, 0x11111111);
|
||||
tcg_gen_muli_tl(tmp, tmp, 6);
|
||||
ret = do_unit(ctx, rt, tmp, load_gpr(ctx, r2), cf, false,
|
||||
is_i ? tcg_gen_add_tl : tcg_gen_sub_tl);
|
||||
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_ds(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn *di)
|
||||
{
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned r1 = extract32(insn, 16, 5);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 0, 5);
|
||||
TCGv dest, add1, add2, addc, zero, in1, in2;
|
||||
|
||||
nullify_over(ctx);
|
||||
|
||||
in1 = load_gpr(ctx, r1);
|
||||
in2 = load_gpr(ctx, r2);
|
||||
|
||||
add1 = tcg_temp_new();
|
||||
add2 = tcg_temp_new();
|
||||
addc = tcg_temp_new();
|
||||
dest = tcg_temp_new();
|
||||
zero = tcg_const_tl(0);
|
||||
|
||||
/* Form R1 << 1 | PSW[CB]{8}. */
|
||||
tcg_gen_add_tl(add1, in1, in1);
|
||||
tcg_gen_add_tl(add1, add1, cpu_psw_cb_msb);
|
||||
|
||||
/* Add or subtract R2, depending on PSW[V]. Proper computation of
|
||||
carry{8} requires that we subtract via + ~R2 + 1, as described in
|
||||
the manual. By extracting and masking V, we can produce the
|
||||
proper inputs to the addition without movcond. */
|
||||
tcg_gen_sari_tl(addc, cpu_psw_v, TARGET_LONG_BITS - 1);
|
||||
tcg_gen_xor_tl(add2, in2, addc);
|
||||
tcg_gen_andi_tl(addc, addc, 1);
|
||||
/* ??? This is only correct for 32-bit. */
|
||||
tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
|
||||
tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
|
||||
|
||||
tcg_temp_free(addc);
|
||||
tcg_temp_free(zero);
|
||||
|
||||
/* Write back the result register. */
|
||||
save_gpr(ctx, rt, dest);
|
||||
|
||||
/* Write back PSW[CB]. */
|
||||
tcg_gen_xor_tl(cpu_psw_cb, add1, add2);
|
||||
tcg_gen_xor_tl(cpu_psw_cb, cpu_psw_cb, dest);
|
||||
|
||||
/* Write back PSW[V] for the division step. */
|
||||
tcg_gen_neg_tl(cpu_psw_v, cpu_psw_cb_msb);
|
||||
tcg_gen_xor_tl(cpu_psw_v, cpu_psw_v, in2);
|
||||
|
||||
/* Install the new nullification. */
|
||||
if (cf) {
|
||||
TCGv sv;
|
||||
TCGV_UNUSED(sv);
|
||||
if (cf >> 1 == 6) {
|
||||
/* ??? The lshift is supposed to contribute to overflow. */
|
||||
sv = do_add_sv(ctx, dest, add1, add2);
|
||||
}
|
||||
ctx->null_cond = do_cond(cf, dest, cpu_psw_cb_msb, sv);
|
||||
}
|
||||
|
||||
tcg_temp_free(add1);
|
||||
tcg_temp_free(add2);
|
||||
tcg_temp_free(dest);
|
||||
|
||||
return nullify_end(ctx, NO_EXIT);
|
||||
}
|
||||
|
||||
static const DisasInsn table_arith_log[] = {
|
||||
{ 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */
|
||||
{ 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */
|
||||
{ 0x08000000u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_andc_tl },
|
||||
{ 0x08000200u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_and_tl },
|
||||
{ 0x08000240u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_or_tl },
|
||||
{ 0x08000280u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_xor_tl },
|
||||
{ 0x08000880u, 0xfc000fe0u, trans_cmpclr },
|
||||
{ 0x08000380u, 0xfc000fe0u, trans_uxor },
|
||||
{ 0x08000980u, 0xfc000fa0u, trans_uaddcm },
|
||||
{ 0x08000b80u, 0xfc1f0fa0u, trans_dcor },
|
||||
{ 0x08000440u, 0xfc000fe0u, trans_ds },
|
||||
{ 0x08000700u, 0xfc0007e0u, trans_add }, /* add */
|
||||
{ 0x08000400u, 0xfc0006e0u, trans_sub }, /* sub; sub,b; sub,tsv */
|
||||
{ 0x080004c0u, 0xfc0007e0u, trans_sub }, /* sub,tc; sub,tsv,tc */
|
||||
{ 0x08000200u, 0xfc000320u, trans_add }, /* shladd */
|
||||
};
|
||||
|
||||
static ExitStatus trans_addi(DisasContext *ctx, uint32_t insn)
|
||||
{
|
||||
target_long im = low_sextract(insn, 0, 11);
|
||||
unsigned e1 = extract32(insn, 11, 1);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 16, 5);
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
unsigned o1 = extract32(insn, 26, 1);
|
||||
TCGv tcg_im, tcg_r2;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
|
||||
tcg_im = load_const(ctx, im);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_add(ctx, rt, tcg_im, tcg_r2, 0, false, e1, !o1, false, cf);
|
||||
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_subi(DisasContext *ctx, uint32_t insn)
|
||||
{
|
||||
target_long im = low_sextract(insn, 0, 11);
|
||||
unsigned e1 = extract32(insn, 11, 1);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 16, 5);
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
TCGv tcg_im, tcg_r2;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
|
||||
tcg_im = load_const(ctx, im);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_sub(ctx, rt, tcg_im, tcg_r2, e1, false, false, cf);
|
||||
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_cmpiclr(DisasContext *ctx, uint32_t insn)
|
||||
{
|
||||
target_long im = low_sextract(insn, 0, 11);
|
||||
unsigned cf = extract32(insn, 12, 4);
|
||||
unsigned rt = extract32(insn, 16, 5);
|
||||
unsigned r2 = extract32(insn, 21, 5);
|
||||
TCGv tcg_im, tcg_r2;
|
||||
ExitStatus ret;
|
||||
|
||||
if (cf) {
|
||||
nullify_over(ctx);
|
||||
}
|
||||
|
||||
tcg_im = load_const(ctx, im);
|
||||
tcg_r2 = load_gpr(ctx, r2);
|
||||
ret = do_cmpclr(ctx, rt, tcg_im, tcg_r2, cf);
|
||||
|
||||
return nullify_end(ctx, ret);
|
||||
}
|
||||
|
||||
static ExitStatus trans_ldil(DisasContext *ctx, uint32_t insn)
|
||||
{
|
||||
unsigned rt = extract32(insn, 21, 5);
|
||||
target_long i = assemble_21(insn);
|
||||
TCGv tcg_rt = dest_gpr(ctx, rt);
|
||||
|
||||
tcg_gen_movi_tl(tcg_rt, i);
|
||||
save_gpr(ctx, rt, tcg_rt);
|
||||
cond_free(&ctx->null_cond);
|
||||
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus trans_addil(DisasContext *ctx, uint32_t insn)
|
||||
{
|
||||
unsigned rt = extract32(insn, 21, 5);
|
||||
target_long i = assemble_21(insn);
|
||||
TCGv tcg_rt = load_gpr(ctx, rt);
|
||||
TCGv tcg_r1 = dest_gpr(ctx, 1);
|
||||
|
||||
tcg_gen_addi_tl(tcg_r1, tcg_rt, i);
|
||||
save_gpr(ctx, 1, tcg_r1);
|
||||
cond_free(&ctx->null_cond);
|
||||
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus trans_ldo(DisasContext *ctx, uint32_t insn)
|
||||
{
|
||||
unsigned rb = extract32(insn, 21, 5);
|
||||
unsigned rt = extract32(insn, 16, 5);
|
||||
target_long i = assemble_16(insn);
|
||||
TCGv tcg_rt = dest_gpr(ctx, rt);
|
||||
|
||||
/* Special case rb == 0, for the LDI pseudo-op.
|
||||
The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
|
||||
if (rb == 0) {
|
||||
tcg_gen_movi_tl(tcg_rt, i);
|
||||
} else {
|
||||
tcg_gen_addi_tl(tcg_rt, cpu_gr[rb], i);
|
||||
}
|
||||
save_gpr(ctx, rt, tcg_rt);
|
||||
cond_free(&ctx->null_cond);
|
||||
|
||||
return NO_EXIT;
|
||||
}
|
||||
|
||||
static ExitStatus translate_table_int(DisasContext *ctx, uint32_t insn,
|
||||
const DisasInsn table[], size_t n)
|
||||
{
|
||||
|
|
@ -463,6 +1330,21 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
uint32_t opc = extract32(insn, 26, 6);
|
||||
|
||||
switch (opc) {
|
||||
case 0x02:
|
||||
return translate_table(ctx, insn, table_arith_log);
|
||||
case 0x08:
|
||||
return trans_ldil(ctx, insn);
|
||||
case 0x0A:
|
||||
return trans_addil(ctx, insn);
|
||||
case 0x0D:
|
||||
return trans_ldo(ctx, insn);
|
||||
case 0x24:
|
||||
return trans_cmpiclr(ctx, insn);
|
||||
case 0x25:
|
||||
return trans_subi(ctx, insn);
|
||||
case 0x2C:
|
||||
case 0x2D:
|
||||
return trans_addi(ctx, insn);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue