softfloat: Specialize udiv_qrnnd for x86_64
The ISA has a 128/64-bit division instruction. Tested-by: Emilio G. Cota <cota@braap.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -637,6 +637,11 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b)
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static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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uint64_t n0, uint64_t d)
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uint64_t n0, uint64_t d)
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{
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{
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#if defined(__x86_64__)
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uint64_t q;
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asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
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return q;
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#else
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uint64_t d0, d1, q0, q1, r1, r0, m;
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uint64_t d0, d1, q0, q1, r1, r0, m;
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d0 = (uint32_t)d;
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d0 = (uint32_t)d;
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@ -676,6 +681,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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*r = r0;
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*r = r0;
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return (q1 << 32) | q0;
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return (q1 << 32) | q0;
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#endif
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}
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}
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/*----------------------------------------------------------------------------
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/*----------------------------------------------------------------------------
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