hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS
It's been deprecated since QEMU v3.1. The 40p machine should be used nowadays instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200114114617.28854-1-thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Thomas Huth
David Gibson
parent
79a8733650
commit
b2ce76a073
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@ -10,9 +10,6 @@
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[submodule "roms/openbios"]
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path = roms/openbios
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url = https://git.qemu.org/git/openbios.git
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[submodule "roms/openhackware"]
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path = roms/openhackware
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url = https://git.qemu.org/git/openhackware.git
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[submodule "roms/qemu-palcode"]
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path = roms/qemu-palcode
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url = https://git.qemu.org/git/qemu-palcode.git
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@ -1103,7 +1103,6 @@ F: hw/dma/i82374.c
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F: hw/rtc/m48t59-isa.c
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F: include/hw/isa/pc87312.h
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F: include/hw/rtc/m48t59.h
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F: pc-bios/ppc_rom.bin
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F: tests/acceptance/ppc_prep_40p.py
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sPAPR
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2
Makefile
2
Makefile
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@ -784,7 +784,7 @@ ifdef INSTALL_BLOBS
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BLOBS=bios.bin bios-256k.bin bios-microvm.bin sgabios.bin vgabios.bin vgabios-cirrus.bin \
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vgabios-stdvga.bin vgabios-vmware.bin vgabios-qxl.bin vgabios-virtio.bin \
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vgabios-ramfb.bin vgabios-bochs-display.bin vgabios-ati.bin \
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ppc_rom.bin openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
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openbios-sparc32 openbios-sparc64 openbios-ppc QEMU,tcx.bin QEMU,cgthree.bin \
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pxe-e1000.rom pxe-eepro100.rom pxe-ne2k_pci.rom \
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pxe-pcnet.rom pxe-rtl8139.rom pxe-virtio.rom \
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efi-e1000.rom efi-eepro100.rom efi-ne2k_pci.rom \
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@ -27,8 +27,7 @@
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#
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# @openfirmware: The interface is defined by the (historical) IEEE
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# 1275-1994 standard. Examples for firmware projects that
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# provide this interface are: OpenBIOS, OpenHackWare,
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# SLOF.
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# provide this interface are: OpenBIOS and SLOF.
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#
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# @uboot: Firmware interface defined by the U-Boot project.
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#
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18
hw/ppc/ppc.c
18
hw/ppc/ppc.c
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@ -1490,24 +1490,6 @@ int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
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}
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/*****************************************************************************/
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/* Debug port */
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void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
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{
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addr &= 0xF;
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switch (addr) {
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case 0:
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printf("%c", val);
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break;
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case 1:
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printf("\n");
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fflush(stdout);
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break;
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case 2:
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printf("Set loglevel to %04" PRIx32 "\n", val);
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qemu_set_log(val | 0x100);
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break;
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}
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}
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int ppc_cpu_pir(PowerPCCPU *cpu)
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{
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384
hw/ppc/prep.c
384
hw/ppc/prep.c
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@ -42,7 +42,7 @@
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#include "hw/loader.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/isa/pc87312.h"
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#include "hw/net/ne2000-isa.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/kvm.h"
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#include "sysemu/qtest.h"
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@ -60,178 +60,9 @@
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#define CFG_ADDR 0xf0000510
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#define BIOS_SIZE (1 * MiB)
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#define BIOS_FILENAME "ppc_rom.bin"
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 13, 13 };
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#define NE2000_NB_MAX 6
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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qemu_irq reset_irq;
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Nvram *nvram;
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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qemu_irq contiguous_map_irq;
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int endian;
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} sysctrl_t;
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enum {
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STATE_HARDFILE = 0x01,
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};
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static sysctrl_t *sysctrl;
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) {
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qemu_irq_raise(sysctrl->reset_irq);
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} else {
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qemu_irq_lower(sysctrl->reset_irq);
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}
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/* Check LE mode */
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if (val & 0x02) {
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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}
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break;
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case 0x0800:
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802:
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803:
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/* Motorola base module status register : read-only */
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break;
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case 0x0808:
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/* Hardfile light register */
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if (val & 1)
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sysctrl->state |= STATE_HARDFILE;
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else
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sysctrl->state &= ~STATE_HARDFILE;
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 1);
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}
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 2);
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}
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break;
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case 0x0814:
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C:
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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" => %02" PRIx32"\n", addr, val);
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break;
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}
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}
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t retval = 0xFF;
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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retval = sysctrl->endian << 1;
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break;
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case 0x0800:
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/* Motorola CPU configuration register */
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retval = 0xEF; /* MPC750 */
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break;
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case 0x0802:
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/* Motorola Base module feature register */
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
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break;
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case 0x0803:
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/* Motorola base module status register */
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retval = 0xE0; /* Standard MPC750 */
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break;
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case 0x080C:
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/* Equipment present register:
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* no L2 cache
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* no upgrade processor
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* no cards in PCI slots
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* SCSI fuse is bad
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*/
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retval = 0x3C;
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break;
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case 0x0810:
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/* Motorola base module extended feature register */
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
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break;
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case 0x0814:
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/* L2 invalidate: don't care */
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break;
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case 0x0818:
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/* Keylock */
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retval = 0x00;
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break;
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case 0x081C:
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/* system control register
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* 7 - 6 / 1 - 0: L2 cache enable
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*/
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retval = sysctrl->syscontrol;
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break;
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case 0x0823:
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/* */
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retval = 0x03; /* no L2 cache */
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break;
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case 0x0850:
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/* I/O map type register */
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retval = sysctrl->contiguous_map;
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break;
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default:
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printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
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break;
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}
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trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
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return retval;
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}
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#define NVRAM_SIZE 0x2000
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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@ -247,17 +78,6 @@ static void ppc_prep_reset(void *opaque)
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cpu_reset(CPU(cpu));
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}
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static const MemoryRegionPortio prep_portio_list[] = {
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/* System control ports */
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{ 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
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{ 0x0800, 0x52, 1,
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.read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
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/* Special port to get debug messages from Open-Firmware */
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{ 0x0F00, 4, 1, .write = PPC_debug_write, },
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PORTIO_END_OF_LIST(),
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};
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static PortioList prep_port_list;
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/*****************************************************************************/
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/* NVRAM helpers */
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@ -397,207 +217,6 @@ static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
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return 0;
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}
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/* PowerPC PREP hardware initialisation */
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static void ppc_prep_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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const char *boot_device = machine->boot_order;
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MemoryRegion *sysmem = get_system_memory();
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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Nvram *m48t59;
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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int linux_boot, i, nb_nics1;
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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uint32_t kernel_base, initrd_base;
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long kernel_size, initrd_size;
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DeviceState *dev;
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PCIHostState *pcihost;
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PCIBus *pci_bus;
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PCIDevice *pci;
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ISABus *isa_bus;
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ISADevice *isa;
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int ppc_boot_device;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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sysctrl = g_malloc0(sizeof(sysctrl_t));
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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for (i = 0; i < machine->smp.cpus; i++) {
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cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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if (env->flags & POWERPC_FLAG_RTC_CLK) {
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/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
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cpu_ppc_tb_init(env, 7812500UL);
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} else {
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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}
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qemu_register_reset(ppc_prep_reset, cpu);
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}
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/* allocate RAM */
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memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
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memory_region_add_subregion(sysmem, 0, ram);
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image_targphys(kernel_filename, kernel_base,
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ram_size - kernel_base);
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if (kernel_size < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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error_report("could not load initial ram disk '%s'",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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ppc_boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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ppc_boot_device = '\0';
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/* For now, OHW cannot boot from the network. */
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for (i = 0; boot_device[i] != '\0'; i++) {
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if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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break;
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}
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}
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if (ppc_boot_device == '\0') {
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error_report("No valid boot device for Mac99 machine");
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exit(1);
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}
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}
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if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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error_report("Only 6xx bus is supported on PREP machine");
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exit(1);
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}
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dev = qdev_create(NULL, "raven-pcihost");
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if (bios_name == NULL) {
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bios_name = BIOS_FILENAME;
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}
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qdev_prop_set_string(dev, "bios-name", bios_name);
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qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
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qdev_prop_set_bit(dev, "is-legacy-prep", true);
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pcihost = PCI_HOST_BRIDGE(dev);
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object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
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qdev_init_nofail(dev);
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pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (pci_bus == NULL) {
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error_report("Couldn't create PCI host controller");
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exit(1);
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}
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sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
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/* PCI -> ISA bridge */
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pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
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cpu = POWERPC_CPU(first_cpu);
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qdev_connect_gpio_out(&pci->qdev, 0,
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cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
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sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
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sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
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sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
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sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
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isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
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/* Super I/O (parallel + serial ports) */
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isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO);
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dev = DEVICE(isa);
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qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
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qdev_init_nofail(dev);
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/* init basic PC hardware */
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pci_vga_init(pci_bus);
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nb_nics1 = nb_nics;
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if (nb_nics1 > NE2000_NB_MAX)
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nb_nics1 = NE2000_NB_MAX;
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for(i = 0; i < nb_nics1; i++) {
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if (nd_table[i].model == NULL) {
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nd_table[i].model = g_strdup("ne2k_isa");
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}
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if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
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isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
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&nd_table[i]);
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} else {
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pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
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}
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}
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||||
|
||||
ide_drive_get(hd, ARRAY_SIZE(hd));
|
||||
for(i = 0; i < MAX_IDE_BUS; i++) {
|
||||
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
|
||||
hd[2 * i],
|
||||
hd[2 * i + 1]);
|
||||
}
|
||||
|
||||
cpu = POWERPC_CPU(first_cpu);
|
||||
sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
|
||||
|
||||
portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
|
||||
portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
|
||||
|
||||
/*
|
||||
* PowerPC control and status register group: unimplemented,
|
||||
* would be at address 0xFEFF0000.
|
||||
*/
|
||||
|
||||
if (machine_usb(machine)) {
|
||||
pci_create_simple(pci_bus, -1, "pci-ohci");
|
||||
}
|
||||
|
||||
m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
|
||||
if (m48t59 == NULL)
|
||||
return;
|
||||
sysctrl->nvram = m48t59;
|
||||
|
||||
/* Initialise NVRAM */
|
||||
PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
|
||||
ppc_boot_device,
|
||||
kernel_base, kernel_size,
|
||||
kernel_cmdline,
|
||||
initrd_base, initrd_size,
|
||||
/* XXX: need an option to load a NVRAM image */
|
||||
0,
|
||||
graphic_width, graphic_height, graphic_depth);
|
||||
}
|
||||
|
||||
static void prep_machine_init(MachineClass *mc)
|
||||
{
|
||||
mc->deprecation_reason = "use 40p machine type instead";
|
||||
mc->desc = "PowerPC PREP platform";
|
||||
mc->init = ppc_prep_init;
|
||||
mc->block_default_type = IF_IDE;
|
||||
mc->max_cpus = MAX_CPUS;
|
||||
mc->default_boot_order = "cad";
|
||||
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602");
|
||||
mc->default_display = "std";
|
||||
}
|
||||
|
||||
static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
|
||||
{
|
||||
uint16_t checksum = *(uint16_t *)opaque;
|
||||
|
|
@ -821,4 +440,3 @@ static void ibm_40p_machine_init(MachineClass *mc)
|
|||
}
|
||||
|
||||
DEFINE_MACHINE("40p", ibm_40p_machine_init)
|
||||
DEFINE_MACHINE("prep", prep_machine_init)
|
||||
|
|
|
|||
|
|
@ -68,7 +68,6 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
|
|||
void ppc40x_core_reset(PowerPCCPU *cpu);
|
||||
void ppc40x_chip_reset(PowerPCCPU *cpu);
|
||||
void ppc40x_system_reset(PowerPCCPU *cpu);
|
||||
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
|
||||
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
|
||||
|
|
|
|||
|
|
@ -4,9 +4,6 @@
|
|||
- The VGA BIOS and the Cirrus VGA BIOS come from the LGPL VGA bios
|
||||
project (http://www.nongnu.org/vgabios/).
|
||||
|
||||
- The PowerPC Open Hack'Ware Open Firmware Compatible BIOS is
|
||||
available at https://repo.or.cz/openhackware.git.
|
||||
|
||||
- OpenBIOS (http://www.openbios.org/) is a free (GPL v2) portable
|
||||
firmware implementation. The goal is to implement a 100% IEEE
|
||||
1275-1994 (referred to as Open Firmware) compliant firmware.
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -270,12 +270,6 @@ machine type instead.
|
|||
These machine types are very old and likely can not be used for live migration
|
||||
from old QEMU versions anymore. A newer machine type should be used instead.
|
||||
|
||||
@subsection prep (PowerPC) (since 3.1)
|
||||
|
||||
This machine type uses an unmaintained firmware, broken in lots of ways,
|
||||
and unable to start post-2004 operating systems. 40p machine type should be
|
||||
used instead.
|
||||
|
||||
@subsection spike_v1.9.1 and spike_v1.10 (since 4.1)
|
||||
|
||||
The version specific Spike machines have been deprecated in favour of the
|
||||
|
|
|
|||
|
|
@ -1729,7 +1729,7 @@ differences are mentioned in the following sections.
|
|||
@section PowerPC System emulator
|
||||
@cindex system emulation (PowerPC)
|
||||
|
||||
Use the executable @file{qemu-system-ppc} to simulate a complete PREP
|
||||
Use the executable @file{qemu-system-ppc} to simulate a complete 40P (PREP)
|
||||
or PowerMac PowerPC system.
|
||||
|
||||
QEMU emulates the following PowerMac peripherals:
|
||||
|
|
@ -1749,7 +1749,7 @@ Non Volatile RAM
|
|||
VIA-CUDA with ADB keyboard and mouse.
|
||||
@end itemize
|
||||
|
||||
QEMU emulates the following PREP peripherals:
|
||||
QEMU emulates the following 40P (PREP) peripherals:
|
||||
|
||||
@itemize @minus
|
||||
@item
|
||||
|
|
@ -1761,7 +1761,7 @@ PCI VGA compatible card with VESA Bochs Extensions
|
|||
@item
|
||||
Floppy disk
|
||||
@item
|
||||
NE2000 network adapters
|
||||
PCnet network adapters
|
||||
@item
|
||||
Serial port
|
||||
@item
|
||||
|
|
@ -1770,12 +1770,9 @@ PREP Non Volatile RAM
|
|||
PC compatible keyboard and mouse.
|
||||
@end itemize
|
||||
|
||||
QEMU uses the Open Hack'Ware Open Firmware Compatible BIOS available at
|
||||
@url{http://perso.magic.fr/l_indien/OpenHackWare/index.htm}.
|
||||
|
||||
Since version 0.9.1, QEMU uses OpenBIOS @url{https://www.openbios.org/}
|
||||
for the g3beige and mac99 PowerMac machines. OpenBIOS is a free (GPL
|
||||
v2) portable firmware implementation. The goal is to implement a 100%
|
||||
for the g3beige and mac99 PowerMac and the 40p machines. OpenBIOS is a free
|
||||
(GPL v2) portable firmware implementation. The goal is to implement a 100%
|
||||
IEEE 1275-1994 (referred to as Open Firmware) compliant firmware.
|
||||
|
||||
@c man begin OPTIONS
|
||||
|
|
@ -1798,8 +1795,6 @@ qemu-system-ppc -prom-env 'auto-boot?=false' \
|
|||
-prom-env 'boot-args=conf=hd:2,\yaboot.conf'
|
||||
@end example
|
||||
|
||||
These variables are not used by Open Hack'Ware.
|
||||
|
||||
@end table
|
||||
|
||||
@c man end
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
Subproject commit c559da7c8eec5e45ef1f67978827af6f0b9546f5
|
||||
|
|
@ -108,30 +108,6 @@ static void test_pc_boot_order(void)
|
|||
test_boot_orders(NULL, read_boot_order_pc, test_cases_pc);
|
||||
}
|
||||
|
||||
static uint8_t read_m48t59(QTestState *qts, uint64_t addr, uint16_t reg)
|
||||
{
|
||||
qtest_writeb(qts, addr, reg & 0xff);
|
||||
qtest_writeb(qts, addr + 1, reg >> 8);
|
||||
return qtest_readb(qts, addr + 3);
|
||||
}
|
||||
|
||||
static uint64_t read_boot_order_prep(QTestState *qts)
|
||||
{
|
||||
return read_m48t59(qts, 0x80000000 + 0x74, 0x34);
|
||||
}
|
||||
|
||||
static const boot_order_test test_cases_prep[] = {
|
||||
{ "", 'c', 'c' },
|
||||
{ "-boot c", 'c', 'c' },
|
||||
{ "-boot d", 'd', 'd' },
|
||||
{}
|
||||
};
|
||||
|
||||
static void test_prep_boot_order(void)
|
||||
{
|
||||
test_boot_orders("prep", read_boot_order_prep, test_cases_prep);
|
||||
}
|
||||
|
||||
static uint64_t read_boot_order_pmac(QTestState *qts)
|
||||
{
|
||||
QFWCFG *fw_cfg = mm_fw_cfg_init(qts, 0xf0000510);
|
||||
|
|
@ -190,7 +166,6 @@ int main(int argc, char *argv[])
|
|||
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
|
||||
qtest_add_func("boot-order/pc", test_pc_boot_order);
|
||||
} else if (strcmp(arch, "ppc") == 0 || strcmp(arch, "ppc64") == 0) {
|
||||
qtest_add_func("boot-order/prep", test_prep_boot_order);
|
||||
qtest_add_func("boot-order/pmac_oldworld",
|
||||
test_pmac_oldworld_boot_order);
|
||||
qtest_add_func("boot-order/pmac_newworld",
|
||||
|
|
|
|||
|
|
@ -189,7 +189,7 @@ int main(int argc, char **argv)
|
|||
add_s390x_tests();
|
||||
} else if (g_str_equal(arch, "ppc64")) {
|
||||
const char *ppcmachines[] = {
|
||||
"pseries", "mac99", "g3beige", "40p", "prep", NULL
|
||||
"pseries", "mac99", "g3beige", "40p", NULL
|
||||
};
|
||||
add_cdrom_param_tests(ppcmachines);
|
||||
} else if (g_str_equal(arch, "sparc")) {
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static const TestCase test_cases[] = {
|
|||
{ "mips64", "malta", 0x10000000, .bswap = true },
|
||||
{ "mips64el", "fulong2e", 0x1fd00000 },
|
||||
{ "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
|
||||
{ "ppc", "prep", 0x80000000, .bswap = true },
|
||||
{ "ppc", "40p", 0x80000000, .bswap = true },
|
||||
{ "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },
|
||||
{ "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" },
|
||||
{ "ppc64", "pseries", (1ULL << 45), .bswap = true, .superio = "i82378" },
|
||||
|
|
|
|||
Loading…
Reference in New Issue