qemu-sparc queue
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAl0b1zUeHG1hcmsuY2F2 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfAloH/30S9U4eRMcsEGu9 MLl3+njCQB5P347mTWmIcCyYW+5pcy/brz4vAiCvRCUmUJX1BaOZ+Lgcf2SCyCMd 6PWYPr0CqC3KuzIxC3IJ6OOYa2Kkj5RLfauwi0yWLXqhbUCvBP3QPG0lPcjgXBkc p5m4DeW4R2zAAZPmluJKNeilTN3ZDyrPw4LUwAHhpA8K7a1VEDsvOcG5rU4vAPcJ Nz/8hWg21QPojyezaRJMSfbcFRtmtESkGRLFYGAT+Zqr2x5WO+U3d3ztINa+meoP mkUcoR5Z98uOjaXmxcShfX0gO983GoyY2k8P9BUTiFJJVpcmxvGntwRk6xeyq2d3 1wBpcH4= =tvjw -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20190702' into staging qemu-sparc queue # gpg: Signature made Tue 02 Jul 2019 23:14:13 BST # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20190702: sunhme: ensure that RX descriptor ring overflow is indicated to client driver sunhme: fix return values from sunhme_receive() during receive packet processing sunhme: flush any queued packets when HME_MAC_RXCFG_ENABLE bit is raised sunhme: fix incorrect constant in sunhme_can_receive() sunhme: add trace event for logging PCI IRQ sun4m: set default display type to TCX Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b2e1bc59f0
@ -44,6 +44,7 @@
|
||||
#define HME_SEBI_STAT 0x100
|
||||
#define HME_SEBI_STAT_LINUXBUG 0x108
|
||||
#define HME_SEB_STAT_RXTOHOST 0x10000
|
||||
#define HME_SEB_STAT_NORXD 0x20000
|
||||
#define HME_SEB_STAT_MIFIRQ 0x800000
|
||||
#define HME_SEB_STAT_HOSTTOTX 0x1000000
|
||||
#define HME_SEB_STAT_TXALL 0x2000000
|
||||
@ -209,6 +210,8 @@ static void sunhme_update_irq(SunHMEState *s)
|
||||
}
|
||||
|
||||
level = (seb ? 1 : 0);
|
||||
trace_sunhme_update_irq(mifmask, mif, sebmask, seb, level);
|
||||
|
||||
pci_set_irq(d, level);
|
||||
}
|
||||
|
||||
@ -371,10 +374,20 @@ static void sunhme_mac_write(void *opaque, hwaddr addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
SunHMEState *s = SUNHME(opaque);
|
||||
uint64_t oldval = s->macregs[addr >> 2];
|
||||
|
||||
trace_sunhme_mac_write(addr, val);
|
||||
|
||||
s->macregs[addr >> 2] = val;
|
||||
|
||||
switch (addr) {
|
||||
case HME_MACI_RXCFG:
|
||||
if (!(oldval & HME_MAC_RXCFG_ENABLE) &&
|
||||
(val & HME_MAC_RXCFG_ENABLE)) {
|
||||
qemu_flush_queued_packets(qemu_get_queue(s->nic));
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint64_t sunhme_mac_read(void *opaque, hwaddr addr,
|
||||
@ -647,7 +660,7 @@ static int sunhme_can_receive(NetClientState *nc)
|
||||
{
|
||||
SunHMEState *s = qemu_get_nic_opaque(nc);
|
||||
|
||||
return s->macregs[HME_MAC_RXCFG_ENABLE >> 2] & HME_MAC_RXCFG_ENABLE;
|
||||
return s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE;
|
||||
}
|
||||
|
||||
static void sunhme_link_status_changed(NetClientState *nc)
|
||||
@ -716,7 +729,7 @@ static ssize_t sunhme_receive(NetClientState *nc, const uint8_t *buf,
|
||||
|
||||
/* Do nothing if MAC RX disabled */
|
||||
if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE)) {
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
trace_sunhme_rx_filter_destmac(buf[0], buf[1], buf[2],
|
||||
@ -745,14 +758,14 @@ static ssize_t sunhme_receive(NetClientState *nc, const uint8_t *buf,
|
||||
/* Didn't match hash filter */
|
||||
trace_sunhme_rx_filter_hash_nomatch();
|
||||
trace_sunhme_rx_filter_reject();
|
||||
return 0;
|
||||
return -1;
|
||||
} else {
|
||||
trace_sunhme_rx_filter_hash_match();
|
||||
}
|
||||
} else {
|
||||
/* Not for us */
|
||||
trace_sunhme_rx_filter_reject();
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
} else {
|
||||
trace_sunhme_rx_filter_promisc_match();
|
||||
@ -775,6 +788,14 @@ static ssize_t sunhme_receive(NetClientState *nc, const uint8_t *buf,
|
||||
pci_dma_read(d, rb + cr * HME_DESC_SIZE, &status, 4);
|
||||
pci_dma_read(d, rb + cr * HME_DESC_SIZE + 4, &buffer, 4);
|
||||
|
||||
/* If we don't own the current descriptor then indicate overflow error */
|
||||
if (!(status & HME_XD_OWN)) {
|
||||
s->sebregs[HME_SEBI_STAT >> 2] |= HME_SEB_STAT_NORXD;
|
||||
sunhme_update_irq(s);
|
||||
trace_sunhme_rx_norxd();
|
||||
return -1;
|
||||
}
|
||||
|
||||
rxoffset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_BYTEOFFSET) >>
|
||||
HME_ERX_CFG_BYTEOFFSET_SHIFT;
|
||||
|
||||
|
||||
@ -359,6 +359,8 @@ sunhme_rx_filter_reject(void) "rejecting incoming frame"
|
||||
sunhme_rx_filter_accept(void) "accepting incoming frame"
|
||||
sunhme_rx_desc(uint32_t addr, int offset, uint32_t status, int len, int cr, int nr) "addr 0x%"PRIx32"(+0x%x) status 0x%"PRIx32 " len %d (ring %d/%d)"
|
||||
sunhme_rx_xsum_calc(uint16_t xsum) "calculated incoming xsum as 0x%x"
|
||||
sunhme_rx_norxd(void) "no free rx descriptors available"
|
||||
sunhme_update_irq(uint32_t mifmask, uint32_t mif, uint32_t sebmask, uint32_t seb, int level) "mifmask: 0x%x mif: 0x%x sebmask: 0x%x seb: 0x%x level: %d"
|
||||
|
||||
# virtio-net.c
|
||||
virtio_net_announce_notify(void) ""
|
||||
|
||||
@ -1406,6 +1406,7 @@ static void ss5_class_init(ObjectClass *oc, void *data)
|
||||
mc->is_default = 1;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo ss5_type = {
|
||||
@ -1424,6 +1425,7 @@ static void ss10_class_init(ObjectClass *oc, void *data)
|
||||
mc->max_cpus = 4;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo ss10_type = {
|
||||
@ -1442,6 +1444,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data)
|
||||
mc->max_cpus = 4;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo ss600mp_type = {
|
||||
@ -1460,6 +1463,7 @@ static void ss20_class_init(ObjectClass *oc, void *data)
|
||||
mc->max_cpus = 4;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo ss20_type = {
|
||||
@ -1477,6 +1481,7 @@ static void voyager_class_init(ObjectClass *oc, void *data)
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo voyager_type = {
|
||||
@ -1494,6 +1499,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data)
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo ss_lx_type = {
|
||||
@ -1511,6 +1517,7 @@ static void ss4_class_init(ObjectClass *oc, void *data)
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo ss4_type = {
|
||||
@ -1528,6 +1535,7 @@ static void scls_class_init(ObjectClass *oc, void *data)
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo scls_type = {
|
||||
@ -1545,6 +1553,7 @@ static void sbook_class_init(ObjectClass *oc, void *data)
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
mc->default_display = "tcx";
|
||||
}
|
||||
|
||||
static const TypeInfo sbook_type = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user