hw: misc, add educational driver
I am using qemu for teaching the Linux kernel at our university. I wrote a simple PCI device that can answer to writes/reads, generate interrupts and perform DMA. As I am dragging it locally over 2 years, I am sending it to you now. Signed-off-by: Jiri Slaby <jslaby@suse.cz> [Fix 32-bit compilation. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Jiri Slaby
Paolo Bonzini
parent
e720677e32
commit
b30934cb52
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@ -599,6 +599,11 @@ F: hw/net/opencores_eth.c
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Devices
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-------
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EDU
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M: Jiri Slaby <jslaby@suse.cz>
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S: Maintained
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F: hw/misc/edu.c
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IDE
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M: Kevin Wolf <kwolf@redhat.com>
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M: Stefan Hajnoczi <stefanha@redhat.com>
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@ -32,3 +32,4 @@ CONFIG_PCI_TESTDEV=y
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CONFIG_NVME_PCI=y
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CONFIG_SD=y
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CONFIG_SDHCI=y
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CONFIG_EDU=y
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@ -0,0 +1,110 @@
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EDU device
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==========
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Copyright (c) 2014-2015 Jiri Slaby
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This document is licensed under the GPLv2 (or later).
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This is an educational device for writing (kernel) drivers. Its original
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intention was to support the Linux kernel lectures taught at the Masaryk
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University. Students are given this virtual device and are expected to write a
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driver with I/Os, IRQs, DMAs and such.
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The devices behaves very similar to the PCI bridge present in the COMBO6 cards
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developed under the Liberouter wings. Both PCI device ID and PCI space is
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inherited from that device.
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Command line switches:
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-device edu[,dma_mask=mask]
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dma_mask makes the virtual device work with DMA addresses with the given
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mask. For educational purposes, the device supports only 28 bits (256 MiB)
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by default. Students shall set dma_mask for the device in the OS driver
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properly.
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PCI specs
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---------
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PCI ID: 1234:11e8
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PCI Region 0:
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I/O memory, 1 MB in size. Users are supposed to communicate with the card
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through this memory.
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MMIO area spec
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--------------
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Only size == 4 accesses are allowed for addresses < 0x80. size == 4 or
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size == 8 for the rest.
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0x00 (RO) : identification (0xRRrr00edu)
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RR -- major version
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rr -- minor version
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0x04 (RW) : card liveness check
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It is a simple value inversion (~ C operator).
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0x08 (RW) : factorial computation
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The stored value is taken and factorial of it is put back here.
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This happens only after factorial bit in the status register (0x20
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below) is cleared.
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0x20 (RW) : status register, bitwise OR
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0x01 -- computing factorial (RO)
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0x80 -- raise interrupt 0x01 after finishing factorial computation
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0x24 (RO) : interrupt status register
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It contains values which raised the interrupt (see interrupt raise
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register below).
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0x60 (WO) : interrupt raise register
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Raise an interrupt. The value will be put to the interrupt status
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register (using bitwise OR).
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0x64 (WO) : interrupt acknowledge register
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Clear an interrupt. The value will be cleared from the interrupt
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status register. This needs to be done from the ISR to stop
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generating interrupts.
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0x80 (RW) : DMA source address
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Where to perform the DMA from.
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0x88 (RW) : DMA destination address
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Where to perform the DMA to.
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0x90 (RW) : DMA transfer count
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The size of the area to perform the DMA on.
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0x98 (RW) : DMA command register, bitwise OR
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0x01 -- start transfer
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0x02 -- direction (0: from RAM to EDU, 1: from EDU to RAM)
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0x04 -- raise interrupt 0x100 after finishing the DMA
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IRQ controller
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--------------
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An IRQ is generated when written to the interrupt raise register. The value
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appears in interrupt status register when the interrupt is raised and has to
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be written to the interrupt acknowledge register to lower it.
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DMA controller
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--------------
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One has to specify, source, destination, size, and start the transfer. One
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4096 bytes long buffer at offset 0x40000 is available in the EDU device. I.e.
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one can perform DMA to/from this space when programmed properly.
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Example of transferring a 100 byte block to and from the buffer using a given
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PCI address 'addr':
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addr -> DMA source address
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0x40000 -> DMA destination address
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100 -> DMA transfer count
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1 -> DMA command register
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while (DMA command register & 1)
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;
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0x40000 -> DMA source address
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addr+100 -> DMA destination address
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100 -> DMA transfer count
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3 -> DMA command register
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while (DMA command register & 1)
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;
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@ -40,3 +40,4 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o
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obj-$(CONFIG_ZYNQ) += zynq_slcr.o
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obj-$(CONFIG_PVPANIC) += pvpanic.o
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obj-$(CONFIG_EDU) += edu.o
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@ -0,0 +1,408 @@
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/*
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* QEMU educational PCI device
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*
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* Copyright (c) 2012-2015 Jiri Slaby
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "hw/pci/pci.h"
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#include "qemu/timer.h"
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#include "qemu/main-loop.h" /* iothread mutex */
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#include "qapi/visitor.h"
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#define EDU(obj) OBJECT_CHECK(EduState, obj, "edu")
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#define FACT_IRQ 0x00000001
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#define DMA_IRQ 0x00000100
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#define DMA_START 0x40000
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#define DMA_SIZE 4096
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typedef struct {
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PCIDevice pdev;
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MemoryRegion mmio;
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QemuThread thread;
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QemuMutex thr_mutex;
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QemuCond thr_cond;
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bool stopping;
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uint32_t addr4;
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uint32_t fact;
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#define EDU_STATUS_COMPUTING 0x01
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#define EDU_STATUS_IRQFACT 0x80
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uint32_t status;
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uint32_t irq_status;
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#define EDU_DMA_RUN 0x1
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#define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1)
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# define EDU_DMA_FROM_PCI 0
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# define EDU_DMA_TO_PCI 1
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#define EDU_DMA_IRQ 0x4
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struct dma_state {
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dma_addr_t src;
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dma_addr_t dst;
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dma_addr_t cnt;
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dma_addr_t cmd;
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} dma;
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QEMUTimer dma_timer;
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char dma_buf[DMA_SIZE];
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uint64_t dma_mask;
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} EduState;
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static void edu_raise_irq(EduState *edu, uint32_t val)
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{
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edu->irq_status |= val;
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if (edu->irq_status) {
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pci_set_irq(&edu->pdev, 1);
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}
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}
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static void edu_lower_irq(EduState *edu, uint32_t val)
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{
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edu->irq_status &= ~val;
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if (!edu->irq_status) {
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pci_set_irq(&edu->pdev, 0);
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}
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}
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static bool within(uint32_t addr, uint32_t start, uint32_t end)
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{
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return start <= addr && addr < end;
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}
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static void edu_check_range(uint32_t addr, uint32_t size1, uint32_t start,
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uint32_t size2)
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{
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uint32_t end1 = addr + size1;
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uint32_t end2 = start + size2;
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if (within(addr, start, end2) &&
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end1 > addr && within(end1, start, end2)) {
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return;
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}
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hw_error("EDU: DMA range 0x%.8x-0x%.8x out of bounds (0x%.8x-0x%.8x)!",
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addr, end1 - 1, start, end2 - 1);
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}
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static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
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{
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dma_addr_t res = addr & edu->dma_mask;
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if (addr != res) {
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printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
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}
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return res;
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}
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static void edu_dma_timer(void *opaque)
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{
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EduState *edu = opaque;
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bool raise_irq = false;
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if (!(edu->dma.cmd & EDU_DMA_RUN)) {
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return;
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}
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if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
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uint32_t dst = edu->dma.dst;
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edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
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dst -= DMA_START;
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pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
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edu->dma_buf + dst, edu->dma.cnt);
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} else {
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uint32_t src = edu->dma.src;
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edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
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src -= DMA_START;
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pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
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edu->dma_buf + src, edu->dma.cnt);
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}
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edu->dma.cmd &= ~EDU_DMA_RUN;
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if (edu->dma.cmd & EDU_DMA_IRQ) {
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raise_irq = true;
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}
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if (raise_irq) {
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edu_raise_irq(edu, DMA_IRQ);
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}
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}
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static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma,
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bool timer)
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{
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if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
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return;
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}
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if (write) {
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*dma = *val;
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} else {
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*val = *dma;
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}
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if (timer) {
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timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
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}
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}
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static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
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{
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EduState *edu = opaque;
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uint64_t val = ~0ULL;
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if (size != 4) {
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return val;
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}
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switch (addr) {
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case 0x00:
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val = 0x010000edu;
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break;
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case 0x04:
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val = edu->addr4;
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break;
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case 0x08:
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qemu_mutex_lock(&edu->thr_mutex);
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val = edu->fact;
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qemu_mutex_unlock(&edu->thr_mutex);
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break;
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case 0x20:
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val = atomic_read(&edu->status);
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break;
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case 0x24:
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val = edu->irq_status;
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break;
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case 0x80:
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dma_rw(edu, false, &val, &edu->dma.src, false);
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break;
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case 0x88:
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dma_rw(edu, false, &val, &edu->dma.dst, false);
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break;
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case 0x90:
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dma_rw(edu, false, &val, &edu->dma.cnt, false);
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break;
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case 0x98:
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dma_rw(edu, false, &val, &edu->dma.cmd, false);
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break;
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}
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return val;
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}
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static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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EduState *edu = opaque;
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if (addr < 0x80 && size != 4) {
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return;
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}
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if (addr >= 0x80 && size != 4 && size != 8) {
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return;
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}
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switch (addr) {
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case 0x04:
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edu->addr4 = ~val;
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break;
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case 0x08:
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if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
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break;
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}
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/* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
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* set in this function and it is under the iothread mutex.
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*/
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qemu_mutex_lock(&edu->thr_mutex);
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edu->fact = val;
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atomic_or(&edu->status, EDU_STATUS_COMPUTING);
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qemu_cond_signal(&edu->thr_cond);
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qemu_mutex_unlock(&edu->thr_mutex);
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break;
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case 0x20:
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if (val & EDU_STATUS_IRQFACT) {
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atomic_or(&edu->status, EDU_STATUS_IRQFACT);
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} else {
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atomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
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}
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break;
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case 0x60:
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edu_raise_irq(edu, val);
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break;
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case 0x64:
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edu_lower_irq(edu, val);
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break;
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case 0x80:
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dma_rw(edu, true, &val, &edu->dma.src, false);
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break;
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case 0x88:
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dma_rw(edu, true, &val, &edu->dma.dst, false);
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break;
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case 0x90:
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dma_rw(edu, true, &val, &edu->dma.cnt, false);
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break;
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case 0x98:
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if (!(val & EDU_DMA_RUN)) {
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break;
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}
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dma_rw(edu, true, &val, &edu->dma.cmd, true);
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break;
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}
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}
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static const MemoryRegionOps edu_mmio_ops = {
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.read = edu_mmio_read,
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.write = edu_mmio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/*
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* We purposedly use a thread, so that users are forced to wait for the status
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* register.
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*/
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static void *edu_fact_thread(void *opaque)
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{
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EduState *edu = opaque;
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while (1) {
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uint32_t val, ret = 1;
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qemu_mutex_lock(&edu->thr_mutex);
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while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
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!edu->stopping) {
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qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
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}
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if (edu->stopping) {
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qemu_mutex_unlock(&edu->thr_mutex);
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break;
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}
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val = edu->fact;
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qemu_mutex_unlock(&edu->thr_mutex);
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while (val > 0) {
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ret *= val--;
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}
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/*
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* We should sleep for a random period here, so that students are
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* forced to check the status properly.
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*/
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qemu_mutex_lock(&edu->thr_mutex);
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edu->fact = ret;
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qemu_mutex_unlock(&edu->thr_mutex);
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atomic_and(&edu->status, ~EDU_STATUS_COMPUTING);
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if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
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qemu_mutex_lock_iothread();
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edu_raise_irq(edu, FACT_IRQ);
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qemu_mutex_unlock_iothread();
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}
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}
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return NULL;
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}
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static int pci_edu_init(PCIDevice *pdev)
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{
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EduState *edu = DO_UPCAST(EduState, pdev, pdev);
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uint8_t *pci_conf = pdev->config;
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timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);
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qemu_mutex_init(&edu->thr_mutex);
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qemu_cond_init(&edu->thr_cond);
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qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
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edu, QEMU_THREAD_JOINABLE);
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pci_config_set_interrupt_pin(pci_conf, 1);
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memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
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"edu-mmio", 1 << 20);
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pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
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return 0;
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}
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static void pci_edu_uninit(PCIDevice *pdev)
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{
|
||||
EduState *edu = DO_UPCAST(EduState, pdev, pdev);
|
||||
|
||||
qemu_mutex_lock(&edu->thr_mutex);
|
||||
edu->stopping = true;
|
||||
qemu_mutex_unlock(&edu->thr_mutex);
|
||||
qemu_cond_signal(&edu->thr_cond);
|
||||
qemu_thread_join(&edu->thread);
|
||||
|
||||
qemu_cond_destroy(&edu->thr_cond);
|
||||
qemu_mutex_destroy(&edu->thr_mutex);
|
||||
|
||||
timer_del(&edu->dma_timer);
|
||||
}
|
||||
|
||||
static void edu_obj_uint64(Object *obj, struct Visitor *v, void *opaque,
|
||||
const char *name, Error **errp)
|
||||
{
|
||||
uint64_t *val = opaque;
|
||||
|
||||
visit_type_uint64(v, val, name, errp);
|
||||
}
|
||||
|
||||
static void edu_instance_init(Object *obj)
|
||||
{
|
||||
EduState *edu = EDU(obj);
|
||||
|
||||
edu->dma_mask = (1UL << 28) - 1;
|
||||
object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64,
|
||||
edu_obj_uint64, NULL, &edu->dma_mask, NULL);
|
||||
}
|
||||
|
||||
static void edu_class_init(ObjectClass *class, void *data)
|
||||
{
|
||||
PCIDeviceClass *k = PCI_DEVICE_CLASS(class);
|
||||
|
||||
k->init = pci_edu_init;
|
||||
k->exit = pci_edu_uninit;
|
||||
k->vendor_id = PCI_VENDOR_ID_QEMU;
|
||||
k->device_id = 0x11e8;
|
||||
k->revision = 0x10;
|
||||
k->class_id = PCI_CLASS_OTHERS;
|
||||
}
|
||||
|
||||
static void pci_edu_register_types(void)
|
||||
{
|
||||
static const TypeInfo edu_info = {
|
||||
.name = "edu",
|
||||
.parent = TYPE_PCI_DEVICE,
|
||||
.instance_size = sizeof(EduState),
|
||||
.instance_init = edu_instance_init,
|
||||
.class_init = edu_class_init,
|
||||
};
|
||||
|
||||
type_register_static(&edu_info);
|
||||
}
|
||||
type_init(pci_edu_register_types)
|
||||
Loading…
Reference in New Issue