target-sh4: Move PVR/PRR/CVR into SuperHCPUClass
They are never changed once initialized, and moving them to the class will allow to inspect them before instantiating. Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -255,6 +255,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
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static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
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{
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SH7750State *s = opaque;
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SuperHCPUClass *scc;
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switch (addr) {
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case SH7750_BCR1_A7:
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@ -288,11 +289,14 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
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case SH7750_CCR_A7:
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return s->ccr;
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case 0x1f000030: /* Processor version */
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return s->cpu->pvr;
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scc = SUPERH_CPU_GET_CLASS(s->cpu);
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return scc->pvr;
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case 0x1f000040: /* Cache version */
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return s->cpu->cvr;
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scc = SUPERH_CPU_GET_CLASS(s->cpu);
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return scc->cvr;
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case 0x1f000044: /* Processor revision */
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return s->cpu->prr;
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scc = SUPERH_CPU_GET_CLASS(s->cpu);
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return scc->prr;
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default:
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error_access("long read", addr);
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abort();
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@ -40,6 +40,9 @@
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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* @name: The name.
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* @pvr: Processor Version Register
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* @prr: Processor Revision Register
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* @cvr: Cache Version Register
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*
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* A SuperH CPU model.
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*/
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@ -52,6 +55,9 @@ typedef struct SuperHCPUClass {
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void (*parent_reset)(CPUState *cpu);
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const char *name;
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uint32_t pvr;
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uint32_t prr;
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uint32_t cvr;
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} SuperHCPUClass;
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/**
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@ -156,9 +156,6 @@ static void sh7750r_cpu_initfn(Object *obj)
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7750R;
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env->pvr = 0x00050000;
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env->prr = 0x00000100;
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env->cvr = 0x00110000;
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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@ -167,6 +164,9 @@ static void sh7750r_class_init(ObjectClass *oc, void *data)
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7750R";
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scc->pvr = 0x00050000;
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scc->prr = 0x00000100;
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scc->cvr = 0x00110000;
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}
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static const TypeInfo sh7750r_type_info = {
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@ -182,9 +182,6 @@ static void sh7751r_cpu_initfn(Object *obj)
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7751R;
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env->pvr = 0x04050005;
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env->prr = 0x00000113;
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env->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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env->features = SH_FEATURE_BCR3_AND_BCR4;
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}
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@ -193,6 +190,9 @@ static void sh7751r_class_init(ObjectClass *oc, void *data)
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7751R";
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scc->pvr = 0x04050005;
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scc->prr = 0x00000113;
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scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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}
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static const TypeInfo sh7751r_type_info = {
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@ -208,9 +208,6 @@ static void sh7785_cpu_initfn(Object *obj)
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CPUSH4State *env = &cpu->env;
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env->id = SH_CPU_SH7785;
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env->pvr = 0x10300700;
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env->prr = 0x00000200;
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env->cvr = 0x71440211;
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env->features = SH_FEATURE_SH4A;
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}
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@ -219,6 +216,9 @@ static void sh7785_class_init(ObjectClass *oc, void *data)
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SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
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scc->name = "SH7785";
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scc->pvr = 0x10300700;
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scc->prr = 0x00000200;
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scc->cvr = 0x71440211;
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}
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static const TypeInfo sh7785_type_info = {
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@ -179,9 +179,6 @@ typedef struct CPUSH4State {
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CPU_COMMON
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int id; /* CPU model */
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uint32_t pvr; /* Processor Version Register */
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uint32_t prr; /* Processor Revision Register */
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uint32_t cvr; /* Cache Version Register */
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void *intc_handle;
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int in_sleep; /* SR_BL ignored during sleep */
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