hw/misc/iotkit-secctl: Add handling for PPCs
The IoTKit Security Controller includes various registers that expose to software the controls for the Peripheral Protection Controllers in the system. Implement these. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-17-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
de343bb632
commit
b3717c23e1
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@ -92,12 +92,41 @@ static const uint8_t iotkit_secctl_ns_idregs[] = {
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0x0d, 0xf0, 0x05, 0xb1,
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};
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/* The register sets for the various PPCs (AHB internal, APB internal,
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* AHB expansion, APB expansion) are all set up so that they are
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* in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs
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* 0, 1, 2, 3 of that type, so we can convert a register address offset
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* into an an index into a PPC array easily.
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*/
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static inline int offset_to_ppc_idx(uint32_t offset)
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{
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return extract32(offset, 2, 2);
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}
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typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc);
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static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn)
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{
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int i;
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for (i = 0; i < IOTS_NUM_APB_PPC; i++) {
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fn(&s->apb[i]);
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}
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for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
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fn(&s->apbexp[i]);
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}
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for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
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fn(&s->ahbexp[i]);
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}
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}
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static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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uint64_t r;
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uint32_t offset = addr & ~0x3;
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IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
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switch (offset) {
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case A_AHBNSPPC0:
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@ -105,34 +134,52 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
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r = 0;
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break;
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case A_SECRESPCFG:
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case A_NSCCFG:
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case A_SECMPCINTSTATUS:
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r = s->secrespcfg;
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break;
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case A_SECPPCINTSTAT:
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r = s->secppcintstat;
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break;
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case A_SECPPCINTEN:
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case A_SECMSCINTSTAT:
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case A_SECMSCINTEN:
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case A_BRGINTSTAT:
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case A_BRGINTEN:
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r = s->secppcinten;
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break;
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case A_AHBNSPPCEXP0:
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case A_AHBNSPPCEXP1:
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case A_AHBNSPPCEXP2:
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case A_AHBNSPPCEXP3:
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r = s->ahbexp[offset_to_ppc_idx(offset)].ns;
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break;
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case A_APBNSPPC0:
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case A_APBNSPPC1:
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r = s->apb[offset_to_ppc_idx(offset)].ns;
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break;
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case A_APBNSPPCEXP0:
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case A_APBNSPPCEXP1:
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case A_APBNSPPCEXP2:
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case A_APBNSPPCEXP3:
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r = s->apbexp[offset_to_ppc_idx(offset)].ns;
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break;
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case A_AHBSPPPCEXP0:
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case A_AHBSPPPCEXP1:
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case A_AHBSPPPCEXP2:
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case A_AHBSPPPCEXP3:
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r = s->apbexp[offset_to_ppc_idx(offset)].sp;
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break;
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case A_APBSPPPC0:
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case A_APBSPPPC1:
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r = s->apb[offset_to_ppc_idx(offset)].sp;
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break;
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case A_APBSPPPCEXP0:
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case A_APBSPPPCEXP1:
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case A_APBSPPPCEXP2:
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case A_APBSPPPCEXP3:
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r = s->apbexp[offset_to_ppc_idx(offset)].sp;
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break;
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case A_NSCCFG:
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case A_SECMPCINTSTATUS:
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case A_SECMSCINTSTAT:
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case A_SECMSCINTEN:
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case A_BRGINTSTAT:
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case A_BRGINTEN:
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case A_NSMSCEXP:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl S block read: "
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@ -180,11 +227,66 @@ static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
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return MEMTX_OK;
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}
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static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc)
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{
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int i;
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for (i = 0; i < ppc->numports; i++) {
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bool v;
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if (extract32(ppc->ns, i, 1)) {
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v = extract32(ppc->nsp, i, 1);
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} else {
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v = extract32(ppc->sp, i, 1);
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}
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qemu_set_irq(ppc->ap[i], v);
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}
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}
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static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t value)
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{
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int i;
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ppc->ns = value & MAKE_64BIT_MASK(0, ppc->numports);
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for (i = 0; i < ppc->numports; i++) {
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qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1));
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}
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iotkit_secctl_update_ppc_ap(ppc);
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}
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static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t value)
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{
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ppc->sp = value & MAKE_64BIT_MASK(0, ppc->numports);
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iotkit_secctl_update_ppc_ap(ppc);
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}
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static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t value)
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{
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ppc->nsp = value & MAKE_64BIT_MASK(0, ppc->numports);
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iotkit_secctl_update_ppc_ap(ppc);
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}
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static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc)
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{
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uint32_t value = ppc->parent->secppcintstat;
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qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1));
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}
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static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc)
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{
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uint32_t value = ppc->parent->secppcinten;
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qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1));
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}
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static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
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uint32_t offset = addr;
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IoTKitSecCtlPPC *ppc;
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trace_iotkit_secctl_s_write(offset, value, size);
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@ -197,33 +299,61 @@ static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr,
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switch (offset) {
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case A_SECRESPCFG:
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case A_NSCCFG:
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value &= 1;
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s->secrespcfg = value;
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qemu_set_irq(s->sec_resp_cfg, s->secrespcfg);
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break;
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case A_SECPPCINTCLR:
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value &= 0x00f000f3;
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foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear);
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break;
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case A_SECPPCINTEN:
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case A_SECMSCINTCLR:
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case A_SECMSCINTEN:
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case A_BRGINTCLR:
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case A_BRGINTEN:
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s->secppcinten = value & 0x00f000f3;
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foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable);
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break;
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case A_AHBNSPPCEXP0:
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case A_AHBNSPPCEXP1:
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case A_AHBNSPPCEXP2:
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case A_AHBNSPPCEXP3:
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ppc = &s->ahbexp[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_ns_write(ppc, value);
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break;
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case A_APBNSPPC0:
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case A_APBNSPPC1:
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ppc = &s->apb[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_ns_write(ppc, value);
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break;
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case A_APBNSPPCEXP0:
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case A_APBNSPPCEXP1:
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case A_APBNSPPCEXP2:
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case A_APBNSPPCEXP3:
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ppc = &s->apbexp[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_ns_write(ppc, value);
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break;
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case A_AHBSPPPCEXP0:
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case A_AHBSPPPCEXP1:
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case A_AHBSPPPCEXP2:
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case A_AHBSPPPCEXP3:
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ppc = &s->ahbexp[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_sp_write(ppc, value);
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break;
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case A_APBSPPPC0:
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case A_APBSPPPC1:
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ppc = &s->apb[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_sp_write(ppc, value);
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break;
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case A_APBSPPPCEXP0:
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case A_APBSPPPCEXP1:
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case A_APBSPPPCEXP2:
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case A_APBSPPPCEXP3:
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ppc = &s->apbexp[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_sp_write(ppc, value);
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break;
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case A_NSCCFG:
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case A_SECMSCINTCLR:
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case A_SECMSCINTEN:
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case A_BRGINTCLR:
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case A_BRGINTEN:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl S block write: "
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"unimplemented offset 0x%x\n", offset);
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@ -265,6 +395,7 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
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uint64_t r;
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uint32_t offset = addr & ~0x3;
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@ -276,15 +407,17 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, hwaddr addr,
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case A_AHBNSPPPCEXP1:
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case A_AHBNSPPPCEXP2:
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case A_AHBNSPPPCEXP3:
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r = s->ahbexp[offset_to_ppc_idx(offset)].nsp;
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break;
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case A_APBNSPPPC0:
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case A_APBNSPPPC1:
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r = s->apb[offset_to_ppc_idx(offset)].nsp;
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break;
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case A_APBNSPPPCEXP0:
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case A_APBNSPPPCEXP1:
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case A_APBNSPPPCEXP2:
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case A_APBNSPPPCEXP3:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl NS block read: "
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"unimplemented offset 0x%x\n", offset);
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r = s->apbexp[offset_to_ppc_idx(offset)].nsp;
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break;
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case A_PID4:
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case A_PID5:
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@ -324,7 +457,9 @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
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uint32_t offset = addr;
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IoTKitSecCtlPPC *ppc;
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trace_iotkit_secctl_ns_write(offset, value, size);
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@ -340,15 +475,20 @@ static MemTxResult iotkit_secctl_ns_write(void *opaque, hwaddr addr,
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case A_AHBNSPPPCEXP1:
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case A_AHBNSPPPCEXP2:
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case A_AHBNSPPPCEXP3:
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ppc = &s->ahbexp[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_nsp_write(ppc, value);
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break;
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case A_APBNSPPPC0:
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case A_APBNSPPPC1:
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ppc = &s->apb[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_nsp_write(ppc, value);
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break;
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case A_APBNSPPPCEXP0:
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case A_APBNSPPPCEXP1:
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case A_APBNSPPPCEXP2:
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case A_APBNSPPPCEXP3:
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qemu_log_mask(LOG_UNIMP,
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"IoTKit SecCtl NS block write: "
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"unimplemented offset 0x%x\n", offset);
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ppc = &s->apbexp[offset_to_ppc_idx(offset)];
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iotkit_secctl_ppc_nsp_write(ppc, value);
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break;
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case A_AHBNSPPPC0:
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case A_PID4:
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@ -397,15 +537,90 @@ static const MemoryRegionOps iotkit_secctl_ns_ops = {
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.impl.max_access_size = 4,
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};
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static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc)
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{
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ppc->ns = 0;
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ppc->sp = 0;
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ppc->nsp = 0;
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}
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static void iotkit_secctl_reset(DeviceState *dev)
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{
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IoTKitSecCtl *s = IOTKIT_SECCTL(dev);
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s->secppcintstat = 0;
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s->secppcinten = 0;
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s->secrespcfg = 0;
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foreach_ppc(s, iotkit_secctl_reset_ppc);
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}
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static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level)
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{
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IoTKitSecCtlPPC *ppc = opaque;
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IoTKitSecCtl *s = IOTKIT_SECCTL(ppc->parent);
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int irqbit = ppc->irq_bit_offset + n;
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s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level);
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}
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static void iotkit_secctl_init_ppc(IoTKitSecCtl *s,
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IoTKitSecCtlPPC *ppc,
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const char *name,
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int numports,
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int irq_bit_offset)
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{
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char *gpioname;
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DeviceState *dev = DEVICE(s);
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ppc->numports = numports;
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ppc->irq_bit_offset = irq_bit_offset;
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ppc->parent = s;
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gpioname = g_strdup_printf("%s_nonsec", name);
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qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports);
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_ap", name);
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qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports);
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_irq_enable", name);
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qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1);
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_irq_clear", name);
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qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1);
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g_free(gpioname);
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gpioname = g_strdup_printf("%s_irq_status", name);
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qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus,
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ppc, gpioname, 1);
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g_free(gpioname);
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}
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static void iotkit_secctl_init(Object *obj)
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{
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IoTKitSecCtl *s = IOTKIT_SECCTL(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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DeviceState *dev = DEVICE(obj);
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int i;
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iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0",
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IOTS_APB_PPC0_NUM_PORTS, 0);
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iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1",
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IOTS_APB_PPC1_NUM_PORTS, 1);
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for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
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IoTKitSecCtlPPC *ppc = &s->apbexp[i];
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char *ppcname = g_strdup_printf("apb_ppcexp%d", i);
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iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i);
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g_free(ppcname);
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}
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for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
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IoTKitSecCtlPPC *ppc = &s->ahbexp[i];
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char *ppcname = g_strdup_printf("ahb_ppcexp%d", i);
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iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i);
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g_free(ppcname);
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}
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qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
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memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops,
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s, "iotkit-secctl-s-regs", 0x1000);
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@ -415,11 +630,32 @@ static void iotkit_secctl_init(Object *obj)
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sysbus_init_mmio(sbd, &s->ns_regs);
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}
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static const VMStateDescription iotkit_secctl_ppc_vmstate = {
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.name = "iotkit-secctl-ppc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ns, IoTKitSecCtlPPC),
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VMSTATE_UINT32(sp, IoTKitSecCtlPPC),
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VMSTATE_UINT32(nsp, IoTKitSecCtlPPC),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static const VMStateDescription iotkit_secctl_vmstate = {
|
||||
.name = "iotkit-secctl",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(secppcintstat, IoTKitSecCtl),
|
||||
VMSTATE_UINT32(secppcinten, IoTKitSecCtl),
|
||||
VMSTATE_UINT32(secrespcfg, IoTKitSecCtl),
|
||||
VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1,
|
||||
iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
|
||||
VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1,
|
||||
iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
|
||||
VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1,
|
||||
iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,28 @@
|
|||
* QEMU interface:
|
||||
* + sysbus MMIO region 0 is the "secure privilege control block" registers
|
||||
* + sysbus MMIO region 1 is the "non-secure privilege control block" registers
|
||||
* + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
|
||||
* should RAZ/WI or bus error
|
||||
* Controlling the 2 APB PPCs in the IoTKit:
|
||||
* + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
|
||||
* + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
|
||||
* + named GPIO outputs apb_ppc{0,1}_irq_enable
|
||||
* + named GPIO outputs apb_ppc{0,1}_irq_clear
|
||||
* + named GPIO inputs apb_ppc{0,1}_irq_status
|
||||
* Controlling each of the 4 expansion APB PPCs which a system using the IoTKit
|
||||
* might provide:
|
||||
* + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
|
||||
* + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
|
||||
* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
|
||||
* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
|
||||
* + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
|
||||
* Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
|
||||
* might provide:
|
||||
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
|
||||
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
|
||||
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
|
||||
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
|
||||
* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
|
||||
*/
|
||||
|
||||
#ifndef IOTKIT_SECCTL_H
|
||||
|
|
@ -26,14 +48,52 @@
|
|||
#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
|
||||
#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_SECCTL)
|
||||
|
||||
typedef struct IoTKitSecCtl {
|
||||
#define IOTS_APB_PPC0_NUM_PORTS 3
|
||||
#define IOTS_APB_PPC1_NUM_PORTS 1
|
||||
#define IOTS_PPC_NUM_PORTS 16
|
||||
#define IOTS_NUM_APB_PPC 2
|
||||
#define IOTS_NUM_APB_EXP_PPC 4
|
||||
#define IOTS_NUM_AHB_EXP_PPC 4
|
||||
|
||||
typedef struct IoTKitSecCtl IoTKitSecCtl;
|
||||
|
||||
/* State and IRQ lines relating to a PPC. For the
|
||||
* PPCs in the IoTKit not all the IRQ lines are used.
|
||||
*/
|
||||
typedef struct IoTKitSecCtlPPC {
|
||||
qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
|
||||
qemu_irq ap[IOTS_PPC_NUM_PORTS];
|
||||
qemu_irq irq_enable;
|
||||
qemu_irq irq_clear;
|
||||
|
||||
uint32_t ns;
|
||||
uint32_t sp;
|
||||
uint32_t nsp;
|
||||
|
||||
/* Number of ports actually present */
|
||||
int numports;
|
||||
/* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
|
||||
int irq_bit_offset;
|
||||
IoTKitSecCtl *parent;
|
||||
} IoTKitSecCtlPPC;
|
||||
|
||||
struct IoTKitSecCtl {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
qemu_irq sec_resp_cfg;
|
||||
|
||||
MemoryRegion s_regs;
|
||||
MemoryRegion ns_regs;
|
||||
} IoTKitSecCtl;
|
||||
|
||||
uint32_t secppcintstat;
|
||||
uint32_t secppcinten;
|
||||
uint32_t secrespcfg;
|
||||
|
||||
IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
|
||||
IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
|
||||
IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue