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target/mips: Add nanoMIPS DSP ASE opcodes

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Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Stefan Markovic 2018-07-13 08:40:22 +02:00 committed by Aleksandar Markovic
parent 261c95a0e9
commit b3979b6fc3
1 changed files with 215 additions and 0 deletions
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215
target/mips/translate.c
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@ -16010,6 +16010,79 @@ enum {
NM_SOV = 0x7a,
};
/* POOL32A5 instruction pool */
enum {
NM_CMP_EQ_PH = 0x00,
NM_CMP_LT_PH = 0x08,
NM_CMP_LE_PH = 0x10,
NM_CMPGU_EQ_QB = 0x18,
NM_CMPGU_LT_QB = 0x20,
NM_CMPGU_LE_QB = 0x28,
NM_CMPGDU_EQ_QB = 0x30,
NM_CMPGDU_LT_QB = 0x38,
NM_CMPGDU_LE_QB = 0x40,
NM_CMPU_EQ_QB = 0x48,
NM_CMPU_LT_QB = 0x50,
NM_CMPU_LE_QB = 0x58,
NM_ADDQ_S_W = 0x60,
NM_SUBQ_S_W = 0x68,
NM_ADDSC = 0x70,
NM_ADDWC = 0x78,
NM_ADDQ_S_PH = 0x01,
NM_ADDQH_R_PH = 0x09,
NM_ADDQH_R_W = 0x11,
NM_ADDU_S_QB = 0x19,
NM_ADDU_S_PH = 0x21,
NM_ADDUH_R_QB = 0x29,
NM_SHRAV_R_PH = 0x31,
NM_SHRAV_R_QB = 0x39,
NM_SUBQ_S_PH = 0x41,
NM_SUBQH_R_PH = 0x49,
NM_SUBQH_R_W = 0x51,
NM_SUBU_S_QB = 0x59,
NM_SUBU_S_PH = 0x61,
NM_SUBUH_R_QB = 0x69,
NM_SHLLV_S_PH = 0x71,
NM_PRECR_SRA_R_PH_W = 0x79,
NM_MULEU_S_PH_QBL = 0x12,
NM_MULEU_S_PH_QBR = 0x1a,
NM_MULQ_RS_PH = 0x22,
NM_MULQ_S_PH = 0x2a,
NM_MULQ_RS_W = 0x32,
NM_MULQ_S_W = 0x3a,
NM_APPEND = 0x42,
NM_MODSUB = 0x52,
NM_SHRAV_R_W = 0x5a,
NM_SHRLV_PH = 0x62,
NM_SHRLV_QB = 0x6a,
NM_SHLLV_QB = 0x72,
NM_SHLLV_S_W = 0x7a,
NM_SHILO = 0x03,
NM_MULEQ_S_W_PHL = 0x04,
NM_MULEQ_S_W_PHR = 0x0c,
NM_MUL_S_PH = 0x05,
NM_PRECR_QB_PH = 0x0d,
NM_PRECRQ_QB_PH = 0x15,
NM_PRECRQ_PH_W = 0x1d,
NM_PRECRQ_RS_PH_W = 0x25,
NM_PRECRQU_S_QB_PH = 0x2d,
NM_PACKRL_PH = 0x35,
NM_PICK_QB = 0x3d,
NM_PICK_PH = 0x45,
NM_SHRA_R_W = 0x5e,
NM_SHRA_R_PH = 0x66,
NM_SHLL_S_PH = 0x76,
NM_SHLL_S_W = 0x7e,
NM_REPL_PH = 0x07
};
/* POOL32A7 instruction pool */
enum {
NM_P_LSX = 0x00,
@ -16199,8 +16272,127 @@ enum {
/* POOL32Axf instruction pool */
enum {
NM_POOL32AXF_1 = 0x01,
NM_POOL32AXF_2 = 0x02,
NM_POOL32AXF_4 = 0x04,
NM_POOL32AXF_5 = 0x05,
NM_POOL32AXF_7 = 0x07,
};
/* POOL32Axf_1 instruction pool */
enum {
NM_POOL32AXF_1_0 = 0x00,
NM_POOL32AXF_1_1 = 0x01,
NM_POOL32AXF_1_3 = 0x03,
NM_POOL32AXF_1_4 = 0x04,
NM_POOL32AXF_1_5 = 0x05,
NM_POOL32AXF_1_7 = 0x07,
};
/* POOL32Axf_2 instruction pool */
enum {
NM_POOL32AXF_2_0_7 = 0x00,
NM_POOL32AXF_2_8_15 = 0x01,
NM_POOL32AXF_2_16_23 = 0x02,
NM_POOL32AXF_2_24_31 = 0x03,
};
/* POOL32Axf_7 instruction pool */
enum {
NM_SHRA_R_QB = 0x0,
NM_SHRL_PH = 0x1,
NM_REPL_QB = 0x2,
};
/* POOL32Axf_1_0 instruction pool */
enum {
NM_MFHI = 0x0,
NM_MFLO = 0x1,
NM_MTHI = 0x2,
NM_MTLO = 0x3,
};
/* POOL32Axf_1_1 instruction pool */
enum {
NM_MTHLIP = 0x0,
NM_SHILOV = 0x1,
};
/* POOL32Axf_1_3 instruction pool */
enum {
NM_RDDSP = 0x0,
NM_WRDSP = 0x1,
NM_EXTP = 0x2,
NM_EXTPDP = 0x3,
};
/* POOL32Axf_1_4 instruction pool */
enum {
NM_SHLL_QB = 0x0,
NM_SHRL_QB = 0x1,
};
/* POOL32Axf_1_5 instruction pool */
enum {
NM_MAQ_S_W_PHR = 0x0,
NM_MAQ_S_W_PHL = 0x1,
NM_MAQ_SA_W_PHR = 0x2,
NM_MAQ_SA_W_PHL = 0x3,
};
/* POOL32Axf_1_7 instruction pool */
enum {
NM_EXTR_W = 0x0,
NM_EXTR_R_W = 0x1,
NM_EXTR_RS_W = 0x2,
NM_EXTR_S_H = 0x3,
};
/* POOL32Axf_2_0_7 instruction pool */
enum {
NM_DPA_W_PH = 0x0,
NM_DPAQ_S_W_PH = 0x1,
NM_DPS_W_PH = 0x2,
NM_DPSQ_S_W_PH = 0x3,
NM_BALIGN = 0x4,
NM_MADD = 0x5,
NM_MULT = 0x6,
NM_EXTRV_W = 0x7,
};
/* POOL32Axf_2_8_15 instruction pool */
enum {
NM_DPAX_W_PH = 0x0,
NM_DPAQ_SA_L_W = 0x1,
NM_DPSX_W_PH = 0x2,
NM_DPSQ_SA_L_W = 0x3,
NM_MADDU = 0x5,
NM_MULTU = 0x6,
NM_EXTRV_R_W = 0x7,
};
/* POOL32Axf_2_16_23 instruction pool */
enum {
NM_DPAU_H_QBL = 0x0,
NM_DPAQX_S_W_PH = 0x1,
NM_DPSU_H_QBL = 0x2,
NM_DPSQX_S_W_PH = 0x3,
NM_EXTPV = 0x4,
NM_MSUB = 0x5,
NM_MULSA_W_PH = 0x6,
NM_EXTRV_RS_W = 0x7,
};
/* POOL32Axf_2_24_31 instruction pool */
enum {
NM_DPAU_H_QBR = 0x0,
NM_DPAQX_SA_W_PH = 0x1,
NM_DPSU_H_QBR = 0x2,
NM_DPSQX_SA_W_PH = 0x3,
NM_EXTPDPV = 0x4,
NM_MSUBU = 0x5,
NM_MULSAQ_S_W_PH = 0x6,
NM_EXTRV_S_H = 0x7,
};
/* POOL32Axf_{4, 5} instruction pool */
@ -16221,6 +16413,29 @@ enum {
NM_WAIT = 0x61,
NM_DERET = 0x71,
NM_ERETX = 0x79,
/* nanoMIPS DSP instructions */
NM_ABSQ_S_QB = 0x00,
NM_ABSQ_S_PH = 0x08,
NM_ABSQ_S_W = 0x10,
NM_PRECEQ_W_PHL = 0x28,
NM_PRECEQ_W_PHR = 0x30,
NM_PRECEQU_PH_QBL = 0x38,
NM_PRECEQU_PH_QBR = 0x48,
NM_PRECEU_PH_QBL = 0x58,
NM_PRECEU_PH_QBR = 0x68,
NM_PRECEQU_PH_QBLA = 0x39,
NM_PRECEQU_PH_QBRA = 0x49,
NM_PRECEU_PH_QBLA = 0x59,
NM_PRECEU_PH_QBRA = 0x69,
NM_REPLV_PH = 0x01,
NM_REPLV_QB = 0x09,
NM_BITREV = 0x18,
NM_INSV = 0x20,
NM_RADDU_W_QB = 0x78,
NM_BITSWAP = 0x05,
NM_WSBH = 0x3d,
};
/* PP.SR instruction pool */