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tcg/arm: Fix SIGILL in tcg_out_qemu_st_direct

Browse Source 
tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns
 tcg: Clean up error paths in alloc_code_gen_buffer_splitwx_memfd
 linux-user/riscv: Adjust vdso signal frame cfa offsets
 linux-user: Fixed cpu restore with pc 0 on SIGBUS
 -----BEGIN PGP SIGNATURE-----
 
 iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmWvk08dHHJpY2hhcmQu
 aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+hSQf6A2h1vn0eVk+GaIUP
 1WN1xaqvN5DmZm8AcQkdqZxdmMZO+zq592zHcZ4RNWlyq8NU93cPCLpMkw4RltLU
 NkHkqXcYIXUx12StJQ4EKuGNyBSu+emkPbkd31KBMM69zDXbugAmPGH7VGn5Mw7R
 8D02D8dvsG/iqmvI8L/ZJFjkrbO3A0AaSdb1Ynkwl6vlLLjpWCqoSFtwv+ZMYyWn
 q9eLzrJ2pUtoO/CDq3WFnODdAh/QUMHKmgj/4YYvGylPIti7eoM24LXGJWQOeUkX
 c0soBB24DEd92jJWjCsYUokcUVQOITOGbNdlhRGrxICNdIapUvVhvLW/IYxeBTlV
 s5zl+g==
 =rNAP
 -----END PGP SIGNATURE-----

Merge tag 'pull-tcg-20240123' of https://gitlab.com/rth7680/qemu into staging

tcg/arm: Fix SIGILL in tcg_out_qemu_st_direct
tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns
tcg: Clean up error paths in alloc_code_gen_buffer_splitwx_memfd
linux-user/riscv: Adjust vdso signal frame cfa offsets
linux-user: Fixed cpu restore with pc 0 on SIGBUS

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmWvk08dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+hSQf6A2h1vn0eVk+GaIUP
# 1WN1xaqvN5DmZm8AcQkdqZxdmMZO+zq592zHcZ4RNWlyq8NU93cPCLpMkw4RltLU
# NkHkqXcYIXUx12StJQ4EKuGNyBSu+emkPbkd31KBMM69zDXbugAmPGH7VGn5Mw7R
# 8D02D8dvsG/iqmvI8L/ZJFjkrbO3A0AaSdb1Ynkwl6vlLLjpWCqoSFtwv+ZMYyWn
# q9eLzrJ2pUtoO/CDq3WFnODdAh/QUMHKmgj/4YYvGylPIti7eoM24LXGJWQOeUkX
# c0soBB24DEd92jJWjCsYUokcUVQOITOGbNdlhRGrxICNdIapUvVhvLW/IYxeBTlV
# s5zl+g==
# =rNAP
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 23 Jan 2024 10:22:07 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240123' of https://gitlab.com/rth7680/qemu:
  tcg/arm: Fix SIGILL in tcg_out_qemu_st_direct
  linux-user/elfload: check PR_GET_DUMPABLE before creating coredump
  linux-user/elfload: test return value of getrlimit
  linux-user/riscv: Adjust vdso signal frame cfa offsets
  tcg/s390x: Fix encoding of VRIc, VRSa, VRSc insns
  linux-user: Fixed cpu restore with pc 0 on SIGBUS
  tcg: Make the cleanup-on-error path unique
  tcg: Remove unreachable code

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-01-25 12:33:33 +00:00
commit b3a5dd0604
8 changed files with 25 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
linux-user/elfload.c
View File

@ -2,6 +2,7 @@
#include "qemu/osdep.h"
#include <sys/param.h>
#include <sys/prctl.h>
#include <sys/resource.h>
#include <sys/shm.h>
@ -4667,9 +4668,14 @@ static int elf_core_dump(int signr, const CPUArchState *env)
init_note_info(&info);
errno = 0;
getrlimit(RLIMIT_CORE, &dumpsize);
if (dumpsize.rlim_cur == 0)
if (prctl(PR_GET_DUMPABLE) == 0) {
return 0;
}
if (getrlimit(RLIMIT_CORE, &dumpsize) == 0 && dumpsize.rlim_cur == 0) {
return 0;
}
corefile = core_dump_filename(ts);

BIN
linux-user/riscv/vdso-32.so
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BIN
linux-user/riscv/vdso-64.so
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Binary file not shown.

8
linux-user/riscv/vdso.S
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@ -101,12 +101,12 @@ endf __vdso_flush_icache
.cfi_startproc simple
.cfi_signal_frame
#define sizeof_reg (__riscv_xlen / 4)
#define sizeof_reg (__riscv_xlen / 8)
#define sizeof_freg 8
#define B_GR (offsetof_uc_mcontext - sizeof_rt_sigframe)
#define B_FR (offsetof_uc_mcontext - sizeof_rt_sigframe + offsetof_freg0)
#define B_GR 0
#define B_FR offsetof_freg0
.cfi_def_cfa 2, sizeof_rt_sigframe
.cfi_def_cfa 2, offsetof_uc_mcontext
/* Return address */
.cfi_return_column 64

5
linux-user/signal.c
View File

@ -925,7 +925,7 @@ static void host_sigsegv_handler(CPUState *cpu, siginfo_t *info,
cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc);
}
static void host_sigbus_handler(CPUState *cpu, siginfo_t *info,
static uintptr_t host_sigbus_handler(CPUState *cpu, siginfo_t *info,
host_sigcontext *uc)
{
uintptr_t pc = host_signal_pc(uc);
@ -947,6 +947,7 @@ static void host_sigbus_handler(CPUState *cpu, siginfo_t *info,
sigprocmask(SIG_SETMASK, host_signal_mask(uc), NULL);
cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc);
}
return pc;
}
static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
@ -974,7 +975,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
host_sigsegv_handler(cpu, info, uc);
return;
case SIGBUS:
host_sigbus_handler(cpu, info, uc);
pc = host_sigbus_handler(cpu, info, uc);
sync_sig = true;
break;
case SIGILL:

3
tcg/arm/tcg-target.c.inc
View File

@ -1662,6 +1662,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
} else {
tcg_out_strd_r(s, h.cond, datalo, h.base, h.index);
}
} else if (h.index < 0) {
tcg_out_st32_12(s, h.cond, datalo, h.base, 0);
tcg_out_st32_12(s, h.cond, datahi, h.base, 4);
} else if (h.index_scratch) {
tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base);
tcg_out_st32_12(s, h.cond, datahi, h.index, 4);

10
tcg/region.c
View File

@ -584,7 +584,9 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp)
buf_rx = mmap(NULL, size, host_prot_read_exec(), MAP_SHARED, fd, 0);
if (buf_rx == MAP_FAILED) {
goto fail_rx;
error_setg_errno(errp, errno,
"failed to map shared memory for execute");
goto fail;
}
close(fd);
@ -594,12 +596,8 @@ static int alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp)
return PROT_READ | PROT_WRITE;
fail_rx:
error_setg_errno(errp, errno, "failed to map shared memory for execute");
fail:
if (buf_rx != MAP_FAILED) {
munmap(buf_rx, size);
}
/* buf_rx is always equal to MAP_FAILED here and does not require cleanup */
if (buf_rw) {
munmap(buf_rw, size);
}

6
tcg/s390x/tcg-target.c.inc
View File

@ -683,7 +683,7 @@ static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op,
tcg_debug_assert(is_vector_reg(v3));
tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
tcg_out16(s, i2);
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12));
}
static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
@ -738,7 +738,7 @@ static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1,
tcg_debug_assert(is_vector_reg(v3));
tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
tcg_out16(s, b2 << 12 | d2);
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
tcg_out16(s, (op & 0x00ff) | RXB(v1, v3, 0, 0) | (m4 << 12));
}
static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
@ -762,7 +762,7 @@ static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
tcg_debug_assert(is_vector_reg(v3));
tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf));
tcg_out16(s, b2 << 12 | d2);
tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
tcg_out16(s, (op & 0x00ff) | RXB(0, v3, 0, 0) | (m4 << 12));
}
static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,