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target/i386: Enable TSX Suspend Load Address Tracking feature

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This instruction aims to give a way to choose which memory accesses
do not need to be tracked in the TSX read set, which is defined as
CPUID.(EAX=7,ECX=0):EDX[bit 16].

The release spec link is as follows:
https://software.intel.com/content/dam/develop/public/us/en/documents/\
architecture-instruction-set-extensions-programming-reference.pdf

The associated kvm patch link is as follows:
https://lore.kernel.org/patchwork/patch/1268026/

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <1593991036-12183-3-git-send-email-cathy.zhang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Cathy Zhang 2020-07-06 07:17:16 +08:00 committed by Paolo Bonzini
parent 5dd13f2a5b
commit b3c7344e33
2 changed files with 3 additions and 1 deletions
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2
target/i386/cpu.c
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@ -987,7 +987,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"avx512-vp2intersect", NULL, "md-clear", NULL, "avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL, NULL, NULL, "serialize", NULL,
NULL, NULL, NULL /* pconfig */, NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, "spec-ctrl", "stibp", NULL, NULL, "spec-ctrl", "stibp",
NULL, "arch-capabilities", "core-capability", "ssbd", NULL, "arch-capabilities", "core-capability", "ssbd",

2
target/i386/cpu.h
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@ -779,6 +779,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
/* SERIALIZE instruction */ /* SERIALIZE instruction */
#define CPUID_7_0_EDX_SERIALIZE (1U << 14) #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
/* TSX Suspend Load Address Tracking instruction */
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
/* Speculation Control */ /* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */ /* Single Thread Indirect Branch Predictors */