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Add function prologue, fix pointer load on Sparc64 host 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-03-08 13:33:42 +00:00
parent 53cd927312
commit b3db875812
3 changed files with 67 additions and 12 deletions
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66
tcg/sparc/tcg-target.c
View File

@ -71,7 +71,6 @@ static const int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = {
TCG_REG_I2,
TCG_REG_I3,
TCG_REG_I4,
TCG_REG_I5,
};
static const int tcg_target_call_iarg_regs[6] = {
@ -161,8 +160,11 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define INSN_RS2(x) (x)
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
#define INSN_COND(x, a) (((x) << 25) | ((a) << 29)
#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
#define COND_A 0x8
#define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
@ -213,6 +215,10 @@ static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
static inline void tcg_out_movi(TCGContext *s, TCGType type,
int ret, tcg_target_long arg)
{
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
if (arg != (arg & 0xffffffff))
fprintf(stderr, "unimplemented %s with constant %ld\n", __func__, arg);
#endif
if (arg == (arg & 0xfff))
tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(TCG_REG_G0) |
INSN_IMM13(arg));
@ -232,6 +238,21 @@ static inline void tcg_out_ld_raw(TCGContext *s, int ret,
INSN_IMM13(arg & 0x3ff));
}
static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
tcg_target_long arg)
{
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
if (arg != (arg & 0xffffffff))
fprintf(stderr, "unimplemented %s with offset %ld\n", __func__, arg);
if (arg != (arg & 0xfff))
tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10));
tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
INSN_IMM13(arg & 0x3ff));
#else
tcg_out_ld_raw(s, ret, arg);
#endif
}
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
{
if (offset == (offset & 0xfff))
@ -290,6 +311,12 @@ static inline void tcg_out_nop(TCGContext *s)
tcg_out32(s, SETHI | INSN_RD(TCG_REG_G0) | 0);
}
static inline void tcg_target_prologue(TCGContext *s)
{
tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
}
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
const int *const_args)
{
@ -297,22 +324,31 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_O0, args[0]);
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_O7) |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
INSN_IMM13(8));
tcg_out_nop(s);
tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
INSN_RS2(TCG_REG_G0));
break;
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
/* direct jump method */
tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_I5, args[0]);
if (ABS(args[0] - (unsigned long)s->code_ptr) ==
(ABS(args[0] - (unsigned long)s->code_ptr) & 0x1fffff)) {
tcg_out32(s, BA |
INSN_OFF22(args[0] - (unsigned long)s->code_ptr));
} else {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, args[0]);
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
INSN_RS2(TCG_REG_G0));
}
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
} else {
/* indirect jump method */
tcg_out_ld_raw(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
INSN_RS2(TCG_REG_G0));
}
tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
INSN_RS2(TCG_REG_G0));
tcg_out_nop(s);
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
break;
@ -323,7 +359,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
& 0x3fffffff));
tcg_out_nop(s);
} else {
tcg_out_ld_raw(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
tcg_out_ld_ptr(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) |
INSN_RS2(TCG_REG_G0));
tcg_out_nop(s);
@ -514,7 +550,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_exit_tb, { } },
{ INDEX_op_goto_tb, { "r" } },
{ INDEX_op_goto_tb, { } },
{ INDEX_op_call, { "ri" } },
{ INDEX_op_jmp, { "ri" } },
{ INDEX_op_br, { } },
@ -596,13 +632,19 @@ void tcg_target_init(TCGContext *s)
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
#endif
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_G1) |
(1 << TCG_REG_G2) |
(1 << TCG_REG_G3) |
(1 << TCG_REG_G4) |
(1 << TCG_REG_G5) |
(1 << TCG_REG_G6) |
(1 << TCG_REG_G7) |
(1 << TCG_REG_O0) |
(1 << TCG_REG_O1) |
(1 << TCG_REG_O2) |
(1 << TCG_REG_O3) |
(1 << TCG_REG_O4) |
(1 << TCG_REG_O5) |
(1 << TCG_REG_O6) |
(1 << TCG_REG_O7));
tcg_regset_clear(s->reserved_regs);

8
tcg/sparc/tcg-target.h
View File

@ -75,10 +75,18 @@ enum {
#define TCG_REG_CALL_STACK TCG_REG_O6
#define TCG_TARGET_STACK_ALIGN 16
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
#define TCG_TARGET_STACK_MINFRAME 176
#else
#define TCG_TARGET_STACK_MINFRAME 92
#endif
/* optional instructions */
//#define TCG_TARGET_HAS_bswap_i32
//#define TCG_TARGET_HAS_bswap_i64
#define TCG_TARGET_NEEDS_PROLOGUE 1
/* Note: must be synced with dyngen-exec.h */
#ifdef HOST_SOLARIS
#define TCG_AREG0 TCG_REG_G2

5
tcg/tcg.c
View File

@ -1685,6 +1685,11 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
macro_op_index = -1;
args = gen_opparam_buf;
op_index = 0;
#ifdef TCG_TARGET_NEEDS_PROLOGUE
tcg_target_prologue(s);
#endif
for(;;) {
opc = gen_opc_buf[op_index];
#ifdef CONFIG_PROFILER