target/riscv: Expose Zvks[c|g] extnesion properties
Expose the properties of ShangMi Algorithm Suite related extensions (Zvks, Zvksc, Zvksg). Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231026151828.754279-10-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -135,7 +135,10 @@ const RISCVIsaExtData isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng),
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ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
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ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
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ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks),
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ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc),
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ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
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ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
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ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
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ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
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ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
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@ -1400,6 +1403,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
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MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false),
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MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false),
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MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false),
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MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false),
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MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false),
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MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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