From b435f3f3d174721382b55bbd0c785ec50c1796a9 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Fri, 20 Mar 2015 12:06:10 +0000 Subject: [PATCH] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 CP0.EntryLo bits 31:30 have to be cleared. Signed-off-by: Leon Alrae Reviewed-by: Aurelien Jarno --- target-mips/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index f6ae0d3aec..2cc58756f2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4964,10 +4964,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif @@ -5019,10 +5019,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif