trace: Remove %s in grlib trace events
Trace events cannot use %s in their format strings because trace backends vary in how they can deference pointers (if at all). Recording const char * values is not meaningful if their contents are not recorded too. Change grlib trace events that rely on strings so that they communicate similar information without using strings. A follow-up patch explains this limitation and updates docs/tracing.txt. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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@ -133,7 +133,7 @@ grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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break;
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}
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trace_grlib_apbuart_unknown_register("write", addr);
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trace_grlib_apbuart_writel_unknown(addr, value);
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}
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static CPUReadMemoryFunc * const grlib_apbuart_read[] = {
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@ -165,15 +165,15 @@ static uint32_t grlib_gptimer_readl(void *opaque, target_phys_addr_t addr)
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/* Unit registers */
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switch (addr) {
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case SCALER_OFFSET:
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trace_grlib_gptimer_readl(-1, "scaler:", unit->scaler);
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trace_grlib_gptimer_readl(-1, addr, unit->scaler);
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return unit->scaler;
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case SCALER_RELOAD_OFFSET:
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trace_grlib_gptimer_readl(-1, "reload:", unit->reload);
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trace_grlib_gptimer_readl(-1, addr, unit->reload);
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return unit->reload;
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case CONFIG_OFFSET:
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trace_grlib_gptimer_readl(-1, "config:", unit->config);
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trace_grlib_gptimer_readl(-1, addr, unit->config);
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return unit->config;
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default:
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@ -189,17 +189,16 @@ static uint32_t grlib_gptimer_readl(void *opaque, target_phys_addr_t addr)
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switch (timer_addr) {
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case COUNTER_OFFSET:
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value = ptimer_get_count(unit->timers[id].ptimer);
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trace_grlib_gptimer_readl(id, "counter value:", value);
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trace_grlib_gptimer_readl(id, addr, value);
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return value;
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case COUNTER_RELOAD_OFFSET:
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value = unit->timers[id].reload;
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trace_grlib_gptimer_readl(id, "reload value:", value);
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trace_grlib_gptimer_readl(id, addr, value);
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return value;
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case CONFIG_OFFSET:
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trace_grlib_gptimer_readl(id, "scaler value:",
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unit->timers[id].config);
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trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
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return unit->timers[id].config;
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default:
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@ -208,7 +207,7 @@ static uint32_t grlib_gptimer_readl(void *opaque, target_phys_addr_t addr)
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}
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trace_grlib_gptimer_unknown_register("read", addr);
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trace_grlib_gptimer_readl(-1, addr, 0);
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return 0;
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}
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@ -226,19 +225,19 @@ grlib_gptimer_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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case SCALER_OFFSET:
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value &= 0xFFFF; /* clean up the value */
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unit->scaler = value;
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trace_grlib_gptimer_writel(-1, "scaler:", unit->scaler);
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trace_grlib_gptimer_writel(-1, addr, unit->scaler);
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return;
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case SCALER_RELOAD_OFFSET:
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value &= 0xFFFF; /* clean up the value */
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unit->reload = value;
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trace_grlib_gptimer_writel(-1, "reload:", unit->reload);
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trace_grlib_gptimer_writel(-1, addr, unit->reload);
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grlib_gptimer_set_scaler(unit, value);
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return;
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case CONFIG_OFFSET:
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/* Read Only (disable timer freeze not supported) */
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trace_grlib_gptimer_writel(-1, "config (Read Only):", 0);
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trace_grlib_gptimer_writel(-1, addr, 0);
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return;
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default:
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@ -253,18 +252,18 @@ grlib_gptimer_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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/* GPTimer registers */
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switch (timer_addr) {
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case COUNTER_OFFSET:
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trace_grlib_gptimer_writel(id, "counter:", value);
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trace_grlib_gptimer_writel(id, addr, value);
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unit->timers[id].counter = value;
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grlib_gptimer_enable(&unit->timers[id]);
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return;
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case COUNTER_RELOAD_OFFSET:
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trace_grlib_gptimer_writel(id, "reload:", value);
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trace_grlib_gptimer_writel(id, addr, value);
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unit->timers[id].reload = value;
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return;
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case CONFIG_OFFSET:
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trace_grlib_gptimer_writel(id, "config:", value);
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trace_grlib_gptimer_writel(id, addr, value);
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if (value & GPTIMER_INT_PENDING) {
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/* clear pending bit */
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@ -297,7 +296,7 @@ grlib_gptimer_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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}
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trace_grlib_gptimer_unknown_register("write", addr);
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trace_grlib_gptimer_writel(-1, addr, value);
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}
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static CPUReadMemoryFunc * const grlib_gptimer_read[] = {
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@ -220,7 +220,7 @@ static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
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return state->extended[cpu];
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}
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trace_grlib_irqmp_unknown_register("read", addr);
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trace_grlib_irqmp_readl_unknown(addr);
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return 0;
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}
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@ -308,7 +308,7 @@ grlib_irqmp_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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return;
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}
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trace_grlib_irqmp_unknown_register("write", addr);
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trace_grlib_irqmp_writel_unknown(addr, value);
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}
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static CPUReadMemoryFunc * const grlib_irqmp_read[] = {
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10
trace-events
10
trace-events
@ -235,19 +235,19 @@ disable grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable
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disable grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
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disable grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x"
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disable grlib_gptimer_hit(int id) "timer:%d HIT"
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disable grlib_gptimer_readl(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
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disable grlib_gptimer_writel(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
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disable grlib_gptimer_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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disable grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
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disable grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
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# hw/grlib_irqmp.c
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disable grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n"
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disable grlib_irqmp_ack(int intno) "interrupt:%d"
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disable grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
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disable grlib_irqmp_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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disable grlib_irqmp_readl_unknown(uint64_t addr) "addr 0x%"PRIx64""
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disable grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
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# hw/grlib_apbuart.c
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disable grlib_apbuart_event(int event) "event:%d"
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disable grlib_apbuart_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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disable grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x"
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# hw/leon3.c
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disable leon3_set_irq(int intno) "Set CPU IRQ %d"
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