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Q800 branch pull request 20230622 

Cleanup to introduce support of MacOS Classic
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Merge tag 'q800-for-8.1-pull-request' of https://github.com/vivier/qemu-m68k into staging

Q800 branch pull request 20230622

Cleanup to introduce support of MacOS Classic

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# gpg: Signature made Thu 22 Jun 2023 09:55:06 AM CEST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [undefined]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* tag 'q800-for-8.1-pull-request' of https://github.com/vivier/qemu-m68k: (24 commits)
  mac_via: fix rtc command decoding for the PRAM seconds registers
  mac_via: fix rtc command decoding from PRAM addresses 0x0 to 0xf
  q800: move macfb device to Q800MachineState
  q800: don't access Nubus bus directly from the mac-nubus-bridge device
  q800: move mac-nubus-bridge device to Q800MachineState
  q800: move SWIM device to Q800MachineState
  q800: move ESP device to Q800MachineState
  q800: move escc_orgate device to Q800MachineState
  q800: move ESCC device to Q800MachineState
  q800: move dp8393x device to Q800MachineState
  hw/net/dp8393x.c: move TYPE_DP8393X and dp8393xState into dp8393x.h
  q800: move VIA2 device to Q800MachineState
  q800: move VIA1 device to Q800MachineState
  q800: reimplement mac-io region aliasing using IO memory region
  q800: introduce mac-io container memory region
  q800: move GLUE device to Q800MachineState
  q800-glue.c: switch TypeInfo registration to use DEFINE_TYPES() macro
  q800: move GLUE device into separate q800-glue.c file
  q800: move ROM memory region to Q800MachineState
  q800: move CPU object into Q800MachineState
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-22 10:18:32 +02:00
parent 67fe6ae41d 532009054b
commit b455ce4c2f
9 changed files with 635 additions and 366 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -1225,6 +1225,7 @@ q800
M: Laurent Vivier <laurent@vivier.eu>
S: Maintained
F: hw/m68k/q800.c
F: hw/m68k/q800-glue.c
F: hw/misc/mac_via.c
F: hw/nubus/*
F: hw/display/macfb.c
@ -1236,6 +1237,8 @@ F: include/hw/misc/mac_via.h
F: include/hw/nubus/*
F: include/hw/display/macfb.h
F: include/hw/block/swim.h
F: include/hw/m68k/q800.h
F: include/hw/m68k/q800-glue.h
virt
M: Laurent Vivier <laurent@vivier.eu>

2
hw/m68k/meson.build
View File

@ -2,7 +2,7 @@ m68k_ss = ss.source_set()
m68k_ss.add(when: 'CONFIG_AN5206', if_true: files('an5206.c', 'mcf5206.c'))
m68k_ss.add(when: 'CONFIG_MCF5208', if_true: files('mcf5208.c', 'mcf_intc.c'))
m68k_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-kbd.c', 'next-cube.c'))
m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c'))
m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c', 'q800-glue.c'))
m68k_ss.add(when: 'CONFIG_M68K_VIRT', if_true: files('virt.c'))
hw_arch += {'m68k': m68k_ss}

249
hw/m68k/q800-glue.c Normal file
View File

@ -0,0 +1,249 @@
/*
* QEMU q800 logic GLUE (General Logic Unit)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/m68k/q800-glue.h"
#include "hw/boards.h"
#include "hw/irq.h"
#include "hw/nmi.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
/*
* The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
* that performs a variety of functions (RAM management, clock generation, ...).
* The GLUE chip receives interrupt requests from various devices,
* assign priority to each, and asserts one or more interrupt line to the
* CPU.
*/
/*
* The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
* controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
* in NetBSD as follows:
*
* A/UX mode (Linux, NetBSD, auxmode GPIO low)
*
* Level 0: Spurious: ignored
* Level 1: Software
* Level 2: VIA2 (except ethernet, sound)
* Level 3: Ethernet
* Level 4: Serial (SCC)
* Level 5: Sound
* Level 6: VIA1
* Level 7: NMIs: parity errors, RESET button, YANCC error
*
* Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
*
* Level 0: Spurious: ignored
* Level 1: VIA1 (clock, ADB)
* Level 2: VIA2 (NuBus, SCSI)
* Level 3:
* Level 4: Serial (SCC)
* Level 5:
* Level 6:
* Level 7: Non-maskable: parity errors, RESET button
*
* Note that despite references to A/UX mode in Linux and NetBSD, at least
* A/UX 3.0.1 still uses Classic mode.
*/
static void GLUE_set_irq(void *opaque, int irq, int level)
{
GLUEState *s = opaque;
int i;
if (s->auxmode) {
/* Classic mode */
switch (irq) {
case GLUE_IRQ_IN_VIA1:
irq = 0;
break;
case GLUE_IRQ_IN_VIA2:
irq = 1;
break;
case GLUE_IRQ_IN_SONIC:
/* Route to VIA2 instead */
qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level);
return;
case GLUE_IRQ_IN_ESCC:
irq = 3;
break;
case GLUE_IRQ_IN_NMI:
irq = 6;
break;
default:
g_assert_not_reached();
}
} else {
/* A/UX mode */
switch (irq) {
case GLUE_IRQ_IN_VIA1:
irq = 5;
break;
case GLUE_IRQ_IN_VIA2:
irq = 1;
break;
case GLUE_IRQ_IN_SONIC:
irq = 2;
break;
case GLUE_IRQ_IN_ESCC:
irq = 3;
break;
case GLUE_IRQ_IN_NMI:
irq = 6;
break;
default:
g_assert_not_reached();
}
}
if (level) {
s->ipr |= 1 << irq;
} else {
s->ipr &= ~(1 << irq);
}
for (i = 7; i >= 0; i--) {
if ((s->ipr >> i) & 1) {
m68k_set_irq_level(s->cpu, i + 1, i + 25);
return;
}
}
m68k_set_irq_level(s->cpu, 0, 0);
}
static void glue_auxmode_set_irq(void *opaque, int irq, int level)
{
GLUEState *s = GLUE(opaque);
s->auxmode = level;
}
static void glue_nmi(NMIState *n, int cpu_index, Error **errp)
{
GLUEState *s = GLUE(n);
/* Hold NMI active for 100ms */
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1);
timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
}
static void glue_nmi_release(void *opaque)
{
GLUEState *s = GLUE(opaque);
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
}
static void glue_reset(DeviceState *dev)
{
GLUEState *s = GLUE(dev);
s->ipr = 0;
s->auxmode = 0;
timer_del(s->nmi_release);
}
static const VMStateDescription vmstate_glue = {
.name = "q800-glue",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8(ipr, GLUEState),
VMSTATE_UINT8(auxmode, GLUEState),
VMSTATE_TIMER_PTR(nmi_release, GLUEState),
VMSTATE_END_OF_LIST(),
},
};
/*
* If the m68k CPU implemented its inbound irq lines as GPIO lines
* rather than via the m68k_set_irq_level() function we would not need
* this cpu link property and could instead provide outbound IRQ lines
* that the board could wire up to the CPU.
*/
static Property glue_properties[] = {
DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *),
DEFINE_PROP_END_OF_LIST(),
};
static void glue_finalize(Object *obj)
{
GLUEState *s = GLUE(obj);
timer_free(s->nmi_release);
}
static void glue_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
GLUEState *s = GLUE(dev);
qdev_init_gpio_in(dev, GLUE_set_irq, 8);
qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1);
qdev_init_gpio_out(dev, s->irqs, 1);
/* NMI release timer */
s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s);
}
static void glue_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
NMIClass *nc = NMI_CLASS(klass);
dc->vmsd = &vmstate_glue;
dc->reset = glue_reset;
device_class_set_props(dc, glue_properties);
nc->nmi_monitor_handler = glue_nmi;
}
static const TypeInfo glue_info_types[] = {
{
.name = TYPE_GLUE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(GLUEState),
.instance_init = glue_init,
.instance_finalize = glue_finalize,
.class_init = glue_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NMI },
{ }
},
},
};
DEFINE_TYPES(glue_info_types)

526
hw/m68k/q800.c
View File

@ -28,7 +28,6 @@
#include "cpu.h"
#include "hw/boards.h"
#include "hw/or-irq.h"
#include "hw/nmi.h"
#include "elf.h"
#include "hw/loader.h"
#include "ui/console.h"
@ -38,6 +37,8 @@
#include "standard-headers/asm-m68k/bootinfo.h"
#include "standard-headers/asm-m68k/bootinfo-mac.h"
#include "bootinfo.h"
#include "hw/m68k/q800.h"
#include "hw/m68k/q800-glue.h"
#include "hw/misc/mac_via.h"
#include "hw/input/adb.h"
#include "hw/nubus/mac-nubus-bridge.h"
@ -58,6 +59,7 @@
#define IO_BASE 0x50000000
#define IO_SLICE 0x00040000
#define IO_SLICE_MASK (IO_SLICE - 1)
#define IO_SIZE 0x04000000
#define VIA_BASE (IO_BASE + 0x00000)
@ -87,240 +89,6 @@
#define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
BIT(0xe))
/*
* The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
* that performs a variety of functions (RAM management, clock generation, ...).
* The GLUE chip receives interrupt requests from various devices,
* assign priority to each, and asserts one or more interrupt line to the
* CPU.
*/
#define TYPE_GLUE "q800-glue"
OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE)
struct GLUEState {
SysBusDevice parent_obj;
M68kCPU *cpu;
uint8_t ipr;
uint8_t auxmode;
qemu_irq irqs[1];
QEMUTimer *nmi_release;
};
#define GLUE_IRQ_IN_VIA1 0
#define GLUE_IRQ_IN_VIA2 1
#define GLUE_IRQ_IN_SONIC 2
#define GLUE_IRQ_IN_ESCC 3
#define GLUE_IRQ_IN_NMI 4
#define GLUE_IRQ_NUBUS_9 0
/*
* The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
* controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
* in NetBSD as follows:
*
* A/UX mode (Linux, NetBSD, auxmode GPIO low)
*
* Level 0: Spurious: ignored
* Level 1: Software
* Level 2: VIA2 (except ethernet, sound)
* Level 3: Ethernet
* Level 4: Serial (SCC)
* Level 5: Sound
* Level 6: VIA1
* Level 7: NMIs: parity errors, RESET button, YANCC error
*
* Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
*
* Level 0: Spurious: ignored
* Level 1: VIA1 (clock, ADB)
* Level 2: VIA2 (NuBus, SCSI)
* Level 3:
* Level 4: Serial (SCC)
* Level 5:
* Level 6:
* Level 7: Non-maskable: parity errors, RESET button
*
* Note that despite references to A/UX mode in Linux and NetBSD, at least
* A/UX 3.0.1 still uses Classic mode.
*/
static void GLUE_set_irq(void *opaque, int irq, int level)
{
GLUEState *s = opaque;
int i;
if (s->auxmode) {
/* Classic mode */
switch (irq) {
case GLUE_IRQ_IN_VIA1:
irq = 0;
break;
case GLUE_IRQ_IN_VIA2:
irq = 1;
break;
case GLUE_IRQ_IN_SONIC:
/* Route to VIA2 instead */
qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level);
return;
case GLUE_IRQ_IN_ESCC:
irq = 3;
break;
case GLUE_IRQ_IN_NMI:
irq = 6;
break;
default:
g_assert_not_reached();
}
} else {
/* A/UX mode */
switch (irq) {
case GLUE_IRQ_IN_VIA1:
irq = 5;
break;
case GLUE_IRQ_IN_VIA2:
irq = 1;
break;
case GLUE_IRQ_IN_SONIC:
irq = 2;
break;
case GLUE_IRQ_IN_ESCC:
irq = 3;
break;
case GLUE_IRQ_IN_NMI:
irq = 6;
break;
default:
g_assert_not_reached();
}
}
if (level) {
s->ipr |= 1 << irq;
} else {
s->ipr &= ~(1 << irq);
}
for (i = 7; i >= 0; i--) {
if ((s->ipr >> i) & 1) {
m68k_set_irq_level(s->cpu, i + 1, i + 25);
return;
}
}
m68k_set_irq_level(s->cpu, 0, 0);
}
static void glue_auxmode_set_irq(void *opaque, int irq, int level)
{
GLUEState *s = GLUE(opaque);
s->auxmode = level;
}
static void glue_nmi(NMIState *n, int cpu_index, Error **errp)
{
GLUEState *s = GLUE(n);
/* Hold NMI active for 100ms */
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1);
timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
}
static void glue_nmi_release(void *opaque)
{
GLUEState *s = GLUE(opaque);
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
}
static void glue_reset(DeviceState *dev)
{
GLUEState *s = GLUE(dev);
s->ipr = 0;
s->auxmode = 0;
timer_del(s->nmi_release);
}
static const VMStateDescription vmstate_glue = {
.name = "q800-glue",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8(ipr, GLUEState),
VMSTATE_UINT8(auxmode, GLUEState),
VMSTATE_TIMER_PTR(nmi_release, GLUEState),
VMSTATE_END_OF_LIST(),
},
};
/*
* If the m68k CPU implemented its inbound irq lines as GPIO lines
* rather than via the m68k_set_irq_level() function we would not need
* this cpu link property and could instead provide outbound IRQ lines
* that the board could wire up to the CPU.
*/
static Property glue_properties[] = {
DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *),
DEFINE_PROP_END_OF_LIST(),
};
static void glue_finalize(Object *obj)
{
GLUEState *s = GLUE(obj);
timer_free(s->nmi_release);
}
static void glue_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
GLUEState *s = GLUE(dev);
qdev_init_gpio_in(dev, GLUE_set_irq, 8);
qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1);
qdev_init_gpio_out(dev, s->irqs, 1);
/* NMI release timer */
s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s);
}
static void glue_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
NMIClass *nc = NMI_CLASS(klass);
dc->vmsd = &vmstate_glue;
dc->reset = glue_reset;
device_class_set_props(dc, glue_properties);
nc->nmi_monitor_handler = glue_nmi;
}
static const TypeInfo glue_info = {
.name = TYPE_GLUE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(GLUEState),
.instance_init = glue_init,
.instance_finalize = glue_finalize,
.class_init = glue_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_NMI },
{ }
},
};
static void main_cpu_reset(void *opaque)
{
@ -360,9 +128,71 @@ static uint8_t fake_mac_rom[] = {
0x60, 0xFE /* bras [self] */
};
static void q800_init(MachineState *machine)
static MemTxResult macio_alias_read(void *opaque, hwaddr addr, uint64_t *data,
unsigned size, MemTxAttrs attrs)
{
M68kCPU *cpu = NULL;
MemTxResult r;
uint32_t val;
addr &= IO_SLICE_MASK;
addr |= IO_BASE;
switch (size) {
case 4:
val = address_space_ldl_be(&address_space_memory, addr, attrs, &r);
break;
case 2:
val = address_space_lduw_be(&address_space_memory, addr, attrs, &r);
break;
case 1:
val = address_space_ldub(&address_space_memory, addr, attrs, &r);
break;
default:
g_assert_not_reached();
}
*data = val;
return r;
}
static MemTxResult macio_alias_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size, MemTxAttrs attrs)
{
MemTxResult r;
addr &= IO_SLICE_MASK;
addr |= IO_BASE;
switch (size) {
case 4:
address_space_stl_be(&address_space_memory, addr, value, attrs, &r);
break;
case 2:
address_space_stw_be(&address_space_memory, addr, value, attrs, &r);
break;
case 1:
address_space_stb(&address_space_memory, addr, value, attrs, &r);
break;
default:
g_assert_not_reached();
}
return r;
}
static const MemoryRegionOps macio_alias_ops = {
.read_with_attrs = macio_alias_read,
.write_with_attrs = macio_alias_write,
.endianness = DEVICE_BIG_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4,
},
};
static void q800_machine_init(MachineState *machine)
{
Q800MachineState *m = Q800_MACHINE(machine);
int linux_boot;
int32_t kernel_size;
uint64_t elf_entry;
@ -370,11 +200,8 @@ static void q800_init(MachineState *machine)
int bios_size;
ram_addr_t initrd_base;
int32_t initrd_size;
MemoryRegion *rom;
MemoryRegion *io;
MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
uint8_t *prom;
const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1;
int i, checksum;
MacFbMode *macfb_mode;
ram_addr_t ram_size = machine->ram_size;
@ -385,14 +212,11 @@ static void q800_init(MachineState *machine)
hwaddr parameters_base;
CPUState *cs;
DeviceState *dev;
DeviceState *via1_dev, *via2_dev;
DeviceState *escc_orgate;
SysBusESPState *sysbus_esp;
ESPState *esp;
SysBusDevice *sysbus;
BusState *adb_bus;
NubusBus *nubus;
DeviceState *glue;
DriveInfo *dinfo;
uint8_t rng_seed[32];
@ -405,58 +229,68 @@ static void q800_init(MachineState *machine)
}
/* init CPUs */
cpu = M68K_CPU(cpu_create(machine->cpu_type));
qemu_register_reset(main_cpu_reset, cpu);
object_initialize_child(OBJECT(machine), "cpu", &m->cpu, machine->cpu_type);
qdev_realize(DEVICE(&m->cpu), NULL, &error_fatal);
qemu_register_reset(main_cpu_reset, &m->cpu);
/* RAM */
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
/*
* Create container for all IO devices
*/
memory_region_init(&m->macio, OBJECT(machine), "mac-io", IO_SLICE);
memory_region_add_subregion(get_system_memory(), IO_BASE, &m->macio);
/*
* Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
* from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
*/
io = g_new(MemoryRegion, io_slice_nb);
for (i = 0; i < io_slice_nb; i++) {
char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1);
memory_region_init_alias(&io[i], NULL, name, get_system_memory(),
IO_BASE, IO_SLICE);
memory_region_add_subregion(get_system_memory(),
IO_BASE + (i + 1) * IO_SLICE, &io[i]);
g_free(name);
}
memory_region_init_io(&m->macio_alias, OBJECT(machine), &macio_alias_ops,
&m->macio, "mac-io.alias", IO_SIZE - IO_SLICE);
memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE,
&m->macio_alias);
/* IRQ Glue */
glue = qdev_new(TYPE_GLUE);
object_property_set_link(OBJECT(glue), "cpu", OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal);
object_initialize_child(OBJECT(machine), "glue", &m->glue, TYPE_GLUE);
object_property_set_link(OBJECT(&m->glue), "cpu", OBJECT(&m->cpu),
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&m->glue), &error_fatal);
/* VIA 1 */
via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1);
object_initialize_child(OBJECT(machine), "via1", &m->via1,
TYPE_MOS6522_Q800_VIA1);
dinfo = drive_get(IF_MTD, 0, 0);
if (dinfo) {
qdev_prop_set_drive(via1_dev, "drive", blk_by_legacy_dinfo(dinfo));
qdev_prop_set_drive(DEVICE(&m->via1), "drive",
blk_by_legacy_dinfo(dinfo));
}
sysbus = SYS_BUS_DEVICE(via1_dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 1, VIA_BASE);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1));
sysbus = SYS_BUS_DEVICE(&m->via1);
sysbus_realize(sysbus, &error_fatal);
memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 1));
sysbus_connect_irq(sysbus, 0,
qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA1));
/* A/UX mode */
qdev_connect_gpio_out(via1_dev, 0,
qdev_get_gpio_in_named(glue, "auxmode", 0));
qdev_connect_gpio_out(DEVICE(&m->via1), 0,
qdev_get_gpio_in_named(DEVICE(&m->glue),
"auxmode", 0));
adb_bus = qdev_get_child_bus(via1_dev, "adb.0");
adb_bus = qdev_get_child_bus(DEVICE(&m->via1), "adb.0");
dev = qdev_new(TYPE_ADB_KEYBOARD);
qdev_realize_and_unref(dev, adb_bus, &error_fatal);
dev = qdev_new(TYPE_ADB_MOUSE);
qdev_realize_and_unref(dev, adb_bus, &error_fatal);
/* VIA 2 */
via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2);
sysbus = SYS_BUS_DEVICE(via2_dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2));
object_initialize_child(OBJECT(machine), "via2", &m->via2,
TYPE_MOS6522_Q800_VIA2);
sysbus = SYS_BUS_DEVICE(&m->via2);
sysbus_realize(sysbus, &error_fatal);
memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE + VIA_SIZE,
sysbus_mmio_get_region(sysbus, 1));
sysbus_connect_irq(sysbus, 0,
qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA2));
/* MACSONIC */
@ -480,16 +314,20 @@ static void q800_init(MachineState *machine)
nd_table[0].macaddr.a[1] = 0x00;
nd_table[0].macaddr.a[2] = 0x07;
dev = qdev_new("dp8393x");
object_initialize_child(OBJECT(machine), "dp8393x", &m->dp8393x,
TYPE_DP8393X);
dev = DEVICE(&m->dp8393x);
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_bit(dev, "big_endian", true);
object_property_set_link(OBJECT(dev), "dma_mr",
OBJECT(get_system_memory()), &error_abort);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, SONIC_BASE);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC));
sysbus_realize(sysbus, &error_fatal);
memory_region_add_subregion(&m->macio, SONIC_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
sysbus_connect_irq(sysbus, 0,
qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_SONIC));
memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
SONIC_PROM_SIZE, &error_fatal);
@ -507,7 +345,9 @@ static void q800_init(MachineState *machine)
/* SCC */
dev = qdev_new(TYPE_ESCC);
object_initialize_child(OBJECT(machine), "escc", &m->escc,
TYPE_ESCC);
dev = DEVICE(&m->escc);
qdev_prop_set_uint32(dev, "disabled", 0);
qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK);
qdev_prop_set_uint32(dev, "it_shift", 1);
@ -517,22 +357,28 @@ static void q800_init(MachineState *machine)
qdev_prop_set_uint32(dev, "chnBtype", 0);
qdev_prop_set_uint32(dev, "chnAtype", 0);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_realize(sysbus, &error_fatal);
/* Logically OR both its IRQs together */
escc_orgate = DEVICE(object_new(TYPE_OR_IRQ));
object_property_set_int(OBJECT(escc_orgate), "num-lines", 2, &error_fatal);
qdev_realize_and_unref(escc_orgate, NULL, &error_fatal);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0));
sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
qdev_connect_gpio_out(escc_orgate, 0,
qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC));
sysbus_mmio_map(sysbus, 0, SCC_BASE);
object_initialize_child(OBJECT(machine), "escc_orgate", &m->escc_orgate,
TYPE_OR_IRQ);
object_property_set_int(OBJECT(&m->escc_orgate), "num-lines", 2,
&error_fatal);
dev = DEVICE(&m->escc_orgate);
qdev_realize(dev, NULL, &error_fatal);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(dev, 0));
sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(dev, 1));
qdev_connect_gpio_out(dev, 0,
qdev_get_gpio_in(DEVICE(&m->glue),
GLUE_IRQ_IN_ESCC));
memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
/* SCSI */
dev = qdev_new(TYPE_SYSBUS_ESP);
sysbus_esp = SYSBUS_ESP(dev);
object_initialize_child(OBJECT(machine), "esp", &m->esp,
TYPE_SYSBUS_ESP);
sysbus_esp = SYSBUS_ESP(&m->esp);
esp = &sysbus_esp->esp;
esp->dma_memory_read = NULL;
esp->dma_memory_write = NULL;
@ -540,40 +386,57 @@ static void q800_init(MachineState *machine)
sysbus_esp->it_shift = 4;
esp->dma_enabled = 1;
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus = SYS_BUS_DEVICE(&m->esp);
sysbus_realize(sysbus, &error_fatal);
/* SCSI and SCSI data IRQs are negative edge triggered */
sysbus_connect_irq(sysbus, 0, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
VIA2_IRQ_SCSI_BIT)));
sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
VIA2_IRQ_SCSI_DATA_BIT)));
sysbus_mmio_map(sysbus, 0, ESP_BASE);
sysbus_mmio_map(sysbus, 1, ESP_PDMA);
sysbus_connect_irq(sysbus, 0,
qemu_irq_invert(
qdev_get_gpio_in(DEVICE(&m->via2),
VIA2_IRQ_SCSI_BIT)));
sysbus_connect_irq(sysbus, 1,
qemu_irq_invert(
qdev_get_gpio_in(DEVICE(&m->via2),
VIA2_IRQ_SCSI_DATA_BIT)));
memory_region_add_subregion(&m->macio, ESP_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(&m->macio, ESP_PDMA - IO_BASE,
sysbus_mmio_get_region(sysbus, 1));
scsi_bus_legacy_handle_cmdline(&esp->bus);
/* SWIM floppy controller */
dev = qdev_new(TYPE_SWIM);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
object_initialize_child(OBJECT(machine), "swim", &m->swim,
TYPE_SWIM);
sysbus = SYS_BUS_DEVICE(&m->swim);
sysbus_realize(sysbus, &error_fatal);
memory_region_add_subregion(&m->macio, SWIM_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
/* NuBus */
dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE);
qdev_prop_set_uint32(dev, "slot-available-mask",
object_initialize_child(OBJECT(machine), "mac-nubus-bridge",
&m->mac_nubus_bridge,
TYPE_MAC_NUBUS_BRIDGE);
sysbus = SYS_BUS_DEVICE(&m->mac_nubus_bridge);
dev = DEVICE(&m->mac_nubus_bridge);
qdev_prop_set_uint32(DEVICE(&m->mac_nubus_bridge), "slot-available-mask",
Q800_NUBUS_SLOTS_AVAILABLE);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
MAC_NUBUS_FIRST_SLOT * NUBUS_SUPER_SLOT_SIZE);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE +
MAC_NUBUS_FIRST_SLOT * NUBUS_SLOT_SIZE);
sysbus_realize(sysbus, &error_fatal);
memory_region_add_subregion(get_system_memory(),
MAC_NUBUS_FIRST_SLOT * NUBUS_SUPER_SLOT_SIZE,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(get_system_memory(),
NUBUS_SLOT_BASE +
MAC_NUBUS_FIRST_SLOT * NUBUS_SLOT_SIZE,
sysbus_mmio_get_region(sysbus, 1));
qdev_connect_gpio_out(dev, 9,
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
qdev_get_gpio_in_named(DEVICE(&m->via2), "nubus-irq",
VIA2_NUBUS_IRQ_INTVIDEO));
for (i = 1; i < VIA2_NUBUS_IRQ_NB; i++) {
qdev_connect_gpio_out(dev, 9 + i,
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
qdev_get_gpio_in_named(DEVICE(&m->via2),
"nubus-irq",
VIA2_NUBUS_IRQ_9 + i));
}
@ -581,15 +444,17 @@ static void q800_init(MachineState *machine)
* Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
* IRQ via GLUE for use by SONIC Ethernet in classic mode
*/
qdev_connect_gpio_out(glue, GLUE_IRQ_NUBUS_9,
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
qdev_connect_gpio_out(DEVICE(&m->glue), GLUE_IRQ_NUBUS_9,
qdev_get_gpio_in_named(DEVICE(&m->via2), "nubus-irq",
VIA2_NUBUS_IRQ_9));
nubus = &NUBUS_BRIDGE(dev)->bus;
nubus = NUBUS_BUS(qdev_get_child_bus(dev, "nubus-bus.0"));
/* framebuffer in nubus slot #9 */
dev = qdev_new(TYPE_NUBUS_MACFB);
object_initialize_child(OBJECT(machine), "macfb", &m->macfb,
TYPE_NUBUS_MACFB);
dev = DEVICE(&m->macfb);
qdev_prop_set_uint32(dev, "slot", 9);
qdev_prop_set_uint32(dev, "width", graphic_width);
qdev_prop_set_uint32(dev, "height", graphic_height);
@ -599,11 +464,11 @@ static void q800_init(MachineState *machine)
} else {
qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_VGA);
}
qdev_realize_and_unref(dev, BUS(nubus), &error_fatal);
qdev_realize(dev, BUS(nubus), &error_fatal);
macfb_mode = (NUBUS_MACFB(dev)->macfb).mode;
cs = CPU(cpu);
cs = CPU(&m->cpu);
if (linux_boot) {
uint64_t high;
void *param_blob, *param_ptr, *param_rng_seed;
@ -642,11 +507,10 @@ static void q800_init(MachineState *machine)
BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride);
BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE);
rom = g_malloc(sizeof(*rom));
memory_region_init_ram_ptr(rom, NULL, "m68k_fake_mac.rom",
memory_region_init_ram_ptr(&m->rom, NULL, "m68k_fake_mac.rom",
sizeof(fake_mac_rom), fake_mac_rom);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
memory_region_set_readonly(&m->rom, true);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
if (kernel_cmdline) {
BOOTINFOSTR(param_ptr, BI_COMMAND_LINE,
@ -688,11 +552,10 @@ static void q800_init(MachineState *machine)
} else {
uint8_t *ptr;
/* allocate and load BIOS */
rom = g_malloc(sizeof(*rom));
memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
memory_region_init_rom(&m->rom, NULL, "m68k_mac.rom", MACROM_SIZE,
&error_abort);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
/* Load MacROM binary */
if (filename) {
@ -719,26 +582,33 @@ static void q800_init(MachineState *machine)
}
static GlobalProperty hw_compat_q800[] = {
{ "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on"},
{ "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
{ "scsi-hd", "vendor", " SEAGATE" },
{ "scsi-hd", "product", " ST225N" },
{ "scsi-hd", "ver", "1.0 " },
{ "scsi-cd", "quirk_mode_page_apple_vendor", "on"},
{ "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on"},
{ "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on"},
{ "scsi-cd", "quirk_mode_page_truncated", "on"},
{ "scsi-cd", "quirk_mode_page_apple_vendor", "on" },
{ "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on" },
{ "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on" },
{ "scsi-cd", "quirk_mode_page_truncated", "on" },
{ "scsi-cd", "vendor", "MATSHITA" },
{ "scsi-cd", "product", "CD-ROM CR-8005" },
{ "scsi-cd", "ver", "1.0k" },
};
static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
static const char *q800_machine_valid_cpu_types[] = {
M68K_CPU_TYPE_NAME("m68040"),
NULL
};
static void q800_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Macintosh Quadra 800";
mc->init = q800_init;
mc->init = q800_machine_init;
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
mc->valid_cpu_types = q800_machine_valid_cpu_types;
mc->max_cpus = 1;
mc->block_default_type = IF_SCSI;
mc->default_ram_id = "m68k_mac.ram";
@ -748,13 +618,13 @@ static void q800_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo q800_machine_typeinfo = {
.name = MACHINE_TYPE_NAME("q800"),
.parent = TYPE_MACHINE,
.instance_size = sizeof(Q800MachineState),
.class_init = q800_machine_class_init,
};
static void q800_machine_register_types(void)
{
type_register_static(&q800_machine_typeinfo);
type_register_static(&glue_info);
}
type_init(q800_machine_register_types)

13
hw/misc/mac_via.c
View File

@ -362,10 +362,10 @@ static void pram_update(MOS6522Q800VIA1State *v1s)
*
* Command byte Register addressed by the command
*
* z0000001 Seconds register 0 (lowest-order byte)
* z0000101 Seconds register 1
* z0001001 Seconds register 2
* z0001101 Seconds register 3 (highest-order byte)
* z00x0001 Seconds register 0 (lowest-order byte)
* z00x0101 Seconds register 1
* z00x1001 Seconds register 2
* z00x1101 Seconds register 3 (highest-order byte)
* 00110001 Test register (write-only)
* 00110101 Write-Protect Register (write-only)
* z010aa01 RAM address 100aa ($10-$13) (first 20 bytes only)
@ -373,6 +373,7 @@ static void pram_update(MOS6522Q800VIA1State *v1s)
* z0111aaa Extended memory designator and sector number
*
* For a read request, z=1, for a write z=0
* The letter x indicates don't care
* The letter a indicates bits whose value depend on what parameter
* RAM byte you want to address
*/
@ -389,7 +390,7 @@ static int via1_rtc_compact_cmd(uint8_t value)
}
if ((value & 0x03) == 0x01) {
value >>= 2;
if ((value & 0x1c) == 0) {
if ((value & 0x18) == 0) {
/* seconds registers */
return read | (REG_0 + (value & 0x03));
} else if ((value == 0x0c) && !read) {
@ -399,7 +400,7 @@ static int via1_rtc_compact_cmd(uint8_t value)
} else if ((value & 0x1c) == 0x08) {
/* RAM address 0x10 to 0x13 */
return read | (REG_PRAM_ADDR + 0x10 + (value & 0x03));
} else if ((value & 0x43) == 0x41) {
} else if ((value & 0x10) == 0x10) {
/* RAM address 0x00 to 0x0f */
return read | (REG_PRAM_ADDR + (value & 0x0f));
}

32
hw/net/dp8393x.c
View File

@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/net/dp8393x.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "net/net.h"
@ -85,7 +86,6 @@ static const char *reg_names[] = {
#define SONIC_MPT 0x2e
#define SONIC_MDT 0x2f
#define SONIC_DCR2 0x3f
#define SONIC_REG_COUNT 0x40
#define SONIC_CR_HTX 0x0001
#define SONIC_CR_TXP 0x0002
@ -139,36 +139,6 @@ static const char *reg_names[] = {
#define SONIC_DESC_EOL 0x0001
#define SONIC_DESC_ADDR 0xFFFE
#define TYPE_DP8393X "dp8393x"
OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X)
struct dp8393xState {
SysBusDevice parent_obj;
/* Hardware */
uint8_t it_shift;
bool big_endian;
bool last_rba_is_full;
qemu_irq irq;
int irq_level;
QEMUTimer *watchdog;
int64_t wt_last_update;
NICConf conf;
NICState *nic;
MemoryRegion mmio;
/* Registers */
uint16_t cam[16][3];
uint16_t regs[SONIC_REG_COUNT];
/* Temporaries */
uint8_t tx_buffer[0x10000];
int loopback_packet;
/* Memory access */
MemoryRegion *dma_mr;
AddressSpace as;
};
/*
* Accessor functions for values which are formed by

50
include/hw/m68k/q800-glue.h Normal file
View File

@ -0,0 +1,50 @@
/*
* QEMU q800 logic GLUE (General Logic Unit)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_Q800_GLUE_H
#define HW_Q800_GLUE_H
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#define TYPE_GLUE "q800-glue"
OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE)
struct GLUEState {
SysBusDevice parent_obj;
M68kCPU *cpu;
uint8_t ipr;
uint8_t auxmode;
qemu_irq irqs[1];
QEMUTimer *nmi_release;
};
#define GLUE_IRQ_IN_VIA1 0
#define GLUE_IRQ_IN_VIA2 1
#define GLUE_IRQ_IN_SONIC 2
#define GLUE_IRQ_IN_ESCC 3
#define GLUE_IRQ_IN_NMI 4
#define GLUE_IRQ_NUBUS_9 0
#endif

66
include/hw/m68k/q800.h Normal file
View File

@ -0,0 +1,66 @@
/*
* QEMU Motorla 680x0 Macintosh hardware System Emulator
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_Q800_H
#define HW_Q800_H
#include "hw/boards.h"
#include "qom/object.h"
#include "target/m68k/cpu-qom.h"
#include "exec/memory.h"
#include "hw/m68k/q800-glue.h"
#include "hw/misc/mac_via.h"
#include "hw/net/dp8393x.h"
#include "hw/char/escc.h"
#include "hw/or-irq.h"
#include "hw/scsi/esp.h"
#include "hw/block/swim.h"
#include "hw/nubus/mac-nubus-bridge.h"
#include "hw/display/macfb.h"
/*
* The main Q800 machine
*/
struct Q800MachineState {
MachineState parent_obj;
M68kCPU cpu;
MemoryRegion rom;
GLUEState glue;
MOS6522Q800VIA1State via1;
MOS6522Q800VIA2State via2;
dp8393xState dp8393x;
ESCCState escc;
OrIRQState escc_orgate;
SysBusESPState esp;
Swim swim;
MacNubusBridge mac_nubus_bridge;
MacfbNubusState macfb;
MemoryRegion macio;
MemoryRegion macio_alias;
};
#define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800")
OBJECT_DECLARE_SIMPLE_TYPE(Q800MachineState, Q800_MACHINE)
#endif

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/*
* QEMU NS SONIC DP8393x netcard
*
* Copyright (c) 2008-2009 Herve Poussineau
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_NET_DP8393X_H
#define HW_NET_DP8393X_H
#include "hw/sysbus.h"
#include "net/net.h"
#include "exec/memory.h"
#define SONIC_REG_COUNT 0x40
#define TYPE_DP8393X "dp8393x"
OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X)
struct dp8393xState {
SysBusDevice parent_obj;
/* Hardware */
uint8_t it_shift;
bool big_endian;
bool last_rba_is_full;
qemu_irq irq;
int irq_level;
QEMUTimer *watchdog;
int64_t wt_last_update;
NICConf conf;
NICState *nic;
MemoryRegion mmio;
/* Registers */
uint16_t cam[16][3];
uint16_t regs[SONIC_REG_COUNT];
/* Temporaries */
uint8_t tx_buffer[0x10000];
int loopback_packet;
/* Memory access */
MemoryRegion *dma_mr;
AddressSpace as;
};
#endif