OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

hw/acpi/piix4: use qdev gpio to wire up smi_irq 

Initialize the SMI IRQ in piix4_pm_init().

The smi_irq can now be wired up directly using a qdev gpio instead
of having to set the IRQ externally in piix4_pm_initfn().

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220528091934.15520-10-mark.cave-ayland@ilande.co.uk>
[PMD: Partially squash 20220528091934.15520-8-mark.cave-ayland@ilande.co.uk]
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland 2022-05-28 10:02:11 +01:00 committed by Philippe Mathieu-Daudé
parent 29786d42ba
commit b49e94424c
4 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/acpi/piix4.c
View File

@ -502,10 +502,11 @@ static void piix4_pm_init(Object *obj)
PIIX4PMState *s = PIIX4_PM(obj);
qdev_init_gpio_out(DEVICE(obj), &s->irq, 1);
qdev_init_gpio_out_named(DEVICE(obj), &s->smi_irq, "smi-irq", 1);
}
PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq smi_irq, bool smm_enabled)
bool smm_enabled)
{
PCIDevice *pci_dev;
DeviceState *dev;
@ -517,7 +518,6 @@ PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
s = PIIX4_PM(dev);
s->smi_irq = smi_irq;
pci_realize_and_unref(pci_dev, bus, &error_fatal);

3
hw/i386/pc_piix.c
View File

@ -283,9 +283,10 @@ static void pc_init1(MachineState *machine,
PIIX4PMState *piix4_pm;
smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, smi_irq,
piix4_pm = piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100,
x86_machine_is_smm_enabled(x86ms));
qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]);
qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_irq);
pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
/* TODO: Populate SPD eeprom data. */
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);

2
hw/isa/piix4.c
View File

@ -311,7 +311,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
if (smbus) {
pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, NULL, 0);
pms = piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, 0);
qdev_connect_gpio_out(DEVICE(pms), 0,
qdev_get_gpio_in_named(dev, "isa", 9));
*smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c"));

2
include/hw/southbridge/piix.h
View File

@ -17,7 +17,7 @@
#include "hw/acpi/piix4.h"
PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq smi_irq, bool smm_enabled);
bool smm_enabled);
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60