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target/loongarch: Adjust the layout of hardware flags bit fields 

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Rui Wang 2022-11-04 12:05:16 +08:00 committed by Song Gao
parent 8752b13060
commit b4bda2006f
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 14 additions and 3 deletions
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9
target/loongarch/cpu.h
View File

@ -14,6 +14,7 @@
#include "qemu/timer.h"
#include "exec/memory.h"
#include "hw/sysbus.h"
#include "cpu-csr.h"
#define IOCSRF_TEMP 0
#define IOCSRF_NODECNT 1
@ -391,6 +392,12 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#endif
}
/*
* LoongArch CPUs hardware flags.
*/
#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
target_ulong *pc,
target_ulong *cs_base,
@ -398,7 +405,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
{
*pc = env->pc;
*cs_base = 0;
*flags = cpu_mmu_index(env, false);
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
}
void loongarch_cpu_list(void);

2
target/loongarch/insn_trans/trans_privileged.c.inc
View File

@ -159,7 +159,7 @@ static const CSRInfo csr_info[] = {
static bool check_plv(DisasContext *ctx)
{
if (ctx->base.tb->flags == MMU_USER_IDX) {
if (ctx->mem_idx == MMU_USER_IDX) {
generate_exception(ctx, EXCCODE_IPE);
return true;
}

6
target/loongarch/translate.c
View File

@ -75,7 +75,11 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
ctx->mem_idx = ctx->base.tb->flags;
if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
ctx->mem_idx = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
} else {
ctx->mem_idx = MMU_DA_IDX;
}
/* Bound the number of insns to execute to those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;