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e2k: fix lmscon, add pci2pci bridge, hack pci into escc, fix compiling without werror

This commit is contained in:
Alibek Omarov 2021-08-23 02:37:53 +03:00
parent db1f69d6b3
commit b588f7d269
12 changed files with 223 additions and 54 deletions
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4
configs/devices/e2k-softmmu/default.mak
View File

@ -7,3 +7,7 @@ CONFIG_IOAPIC=y
CONFIG_PCI=y
CONFIG_ELBRUS_SIM_CONSOLE=y
CONFIG_PCI_IOHUB=y
CONFIG_VGA_CIRRUS=y
CONFIG_VGA_PCI=y
CONFIG_ATI_VGA=y
CONFIG_ESCC_PCI=y

5
hw/char/Kconfig
View File

@ -1,6 +1,11 @@
config ESCC
bool
config ESCC_PCI
bool
depends on PCI
select ESCC
config HTIF
bool

77
hw/char/escc.c
View File

@ -33,6 +33,11 @@
#include "ui/console.h"
#include "trace.h"
#define CONFIG_ESCC_PCI
#ifdef CONFIG_ESCC_PCI
#include "hw/pci/pci.h"
#endif
/*
* Chipset docs:
* "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
@ -878,9 +883,81 @@ static const TypeInfo escc_info = {
.class_init = escc_class_init,
};
#ifdef CONFIG_ESCC_PCI
#define TYPE_ESCC_PCI "escc-pci"
struct ESCCPCIState {
PCIDevice dev;
ESCCState escc;
};
OBJECT_DECLARE_SIMPLE_TYPE(ESCCPCIState, ESCC_PCI)
static void escc_pci_realize(PCIDevice *dev, Error **errp)
{
ESCCPCIState *pci = ESCC_PCI(dev);
ESCCState *s = &pci->escc;
if (!sysbus_realize(SYS_BUS_DEVICE(s), errp)) {
return;
}
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->mmio);
}
static void escc_pci_exit(PCIDevice *dev)
{
/*ESCCPCIState *pci = ESCC_PCI(dev);
ESCCState *s = &pci->escc;
sysbus_unrealize(SYS_BUS_DEVICE(s));*/
}
static void escc_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
pc->realize = escc_pci_realize;
pc->exit = escc_pci_exit;
pc->vendor_id = 0x1fff;
pc->device_id = 0x8019;
pc->revision = 1;
pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
/* dc->vmsd = &vmstate_pci_serial; */
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
static void escc_pci_init(Object *o)
{
ESCCPCIState *ps = ESCC_PCI(o);
object_initialize_child(o, "escc", &ps->escc, TYPE_ESCC);
qdev_alias_all_properties(DEVICE(&ps->escc), o);
}
static const TypeInfo escc_pci_info = {
.name = TYPE_ESCC_PCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(ESCCPCIState),
.instance_init = escc_pci_init,
.class_init = escc_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
#endif /* CONFIG_ESCC_PCI */
static void escc_register_types(void)
{
type_register_static(&escc_info);
#ifdef CONFIG_ESCC_PCI
type_register_static(&escc_pci_info);
#endif /* CONFIG_ESCC_PCI */
}
type_init(escc_register_types)

22
hw/char/lmscon.c
View File

@ -20,6 +20,7 @@
#include "exec/address-spaces.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "hw/char/lmscon.h"
#include "trace.h"
@ -108,20 +109,17 @@ static const MemoryRegionOps lmscon_mem_ops = {
static void lmscon_realize(DeviceState *dev, Error **errp)
{
MemoryRegion *io;
SysBusDevice *sb = SYS_BUS_DEVICE(dev);
LMSCONState *s = LMSCON(dev);
hwaddr base = s->baseaddr + LMS_CONS_DATA_PORT;
const uint64_t size = LMS_TRACE_CNTL_PORT - LMS_CONS_DATA_PORT;
const uint64_t size = LMS_TRACE_CNTL_PORT - LMS_CONS_DATA_PORT + 1;
io = g_malloc(sizeof(*io));
memory_region_init_io(io, OBJECT(dev), &lmscon_mem_ops, s, "lmscon",
size);
memory_region_add_subregion_overlap(get_system_memory(), base, io, 999);
memory_region_init_io(&s->io, OBJECT(dev), &lmscon_mem_ops, s, "lmscon", size);
sysbus_add_io(sb, LMS_CONS_DATA_PORT, &s->io);
sysbus_init_ioports(sb, LMS_CONS_DATA_PORT, size);
}
static Property lmscon_properties[] = {
DEFINE_PROP_UINT64("baseaddr", LMSCONState, baseaddr, 0),
DEFINE_PROP_CHR("chr", LMSCONState, chr),
DEFINE_PROP_END_OF_LIST(),
};
@ -137,10 +135,10 @@ static void lmscon_class_init(ObjectClass *oc, void *data)
}
static TypeInfo lmscon_info = {
.name = TYPE_LMSCON,
.parent = TYPE_DEVICE,
.name = TYPE_LMSCON,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LMSCONState),
.class_init = lmscon_class_init
.class_init = lmscon_class_init
};
static void lmscon_register_types(void)

59
hw/e2k/e2k.c
View File

@ -27,6 +27,8 @@
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "hw/pci/pci_bridge.h"
#include "hw/e2k/e2k.h"
#include "hw/e2k/bootinfo.h"
#include "target/e2k/cpu.h"
@ -77,27 +79,27 @@ static void cpus_init(E2KMachineState *e2kms)
}
}
/*
static void lmscon_init(E2KMachineState *e2kms)
{
DeviceState *dev;
dev = qdev_new(TYPE_LMSCON);
qdev_prop_set_uint64(dev, "baseaddr", E2K_IO_AREA_BASE);
qdev_prop_set_chr(dev, "chr", serial_hd(0));
if (!qdev_realize(dev, NULL, &error_fatal)) {
if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal)) {
error_report("failed to create lmscon");
exit(1);
}
}
*/
static bootblock_struct_t *generate_bootblock(E2KMachineState *e2kms,
ram_addr_t kernel_base, long kernel_size)
{
static bootblock_struct_t bootblock;
boot_info_t *const bootinfo = &bootblock.info;
bios_info_t *const biosinfo = &bootblock.info.bios;
MachineState *ms = MACHINE(e2kms);
memset(&bootblock, 0, sizeof(bootblock));
@ -141,7 +143,6 @@ static bool e2k_kernel_init(E2KMachineState *e2kms, MemoryRegion *rom_memory)
MachineState *ms = MACHINE(e2kms);
uint64_t entry, kernel_high;
long size;
bootblock_struct_t *bootblock;
MemoryRegion *kernel;
if (!ms->kernel_filename)
@ -206,10 +207,42 @@ static void firmware_init(E2KMachineState *e2kms, const char *default_filename,
reset_params.loadaddr = E2K_BIOS_AREA_BASE;
}
static void e2k_gsi_handler(void *opaque, int n, int level)
/*static void e2k_gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
qemu_set_irq(s->ioapic_irq[n], level);
}*/
#define ESCC_CLOCK 2457600
static PCIDevice *pci_init(E2KMachineState *e2kms)
{
PCIDevice *br, *d;
e2kms->bus = iohub_init(TYPE_IOHUB_PCI_HOST_BRIDGE, TYPE_IOHUB_PCI_DEVICE,
&e2kms->iohub,
get_system_memory(), get_system_io());
br = d = pci_new_multifunction(PCI_DEVFN(0, 0), false, "pci-bridge");
qdev_prop_set_uint8(DEVICE(d), PCI_BRIDGE_DEV_PROP_CHASSIS_NR, 1);
pci_realize_and_unref(d, e2kms->bus, &error_fatal);
d = pci_new_multifunction(PCI_DEVFN(2, 2), false, "escc-pci");
qdev_prop_set_uint32(DEVICE(d), "disabled", 0);
qdev_prop_set_uint32(DEVICE(d), "frequency", ESCC_CLOCK);
qdev_prop_set_uint32(DEVICE(d), "it_shift", 1);
qdev_prop_set_chr(DEVICE(d), "chrA", serial_hd(0));
qdev_prop_set_chr(DEVICE(d), "chrB", serial_hd(1));
qdev_prop_set_uint32(DEVICE(d), "chnBtype", escc_serial);
qdev_prop_set_uint32(DEVICE(d), "chnAtype", escc_serial);
pci_realize_and_unref(d, pci_bridge_get_sec_bus(PCI_BRIDGE(br)), &error_fatal);
/* pci_vga_init(); */
return d;
}
static void e2k_machine_init(MachineState *ms)
@ -217,11 +250,9 @@ static void e2k_machine_init(MachineState *ms)
E2KMachineState *e2kms = E2K_MACHINE(ms);
MemoryRegion *rom_memory;
MemoryRegion *ram_below_4g, *ram_above_4g;
qemu_irq *pic;
MemTxAttrs attrs = { };
rom_memory = get_system_memory();
/* Init RAM banks */
if(ms->ram_size > E2K_MLO_SIZE) {
e2kms->above_4g_mem_size = ms->ram_size - E2K_MLO_SIZE;
@ -250,16 +281,12 @@ static void e2k_machine_init(MachineState *ms)
firmware_init(e2kms, "e2k.bin", rom_memory);
e2kms->gsi_state = g_new0(GSIState, 1);
pic = qemu_allocate_irqs(e2k_gsi_handler, e2kms->gsi_state, IOAPIC_NUM_PINS);
qemu_log_mask(LOG_UNIMP, "HI :)\n");
// pic = qemu_allocate_irqs(e2k_gsi_handler, e2kms->gsi_state, IOAPIC_NUM_PINS);
cpus_init(e2kms);
lmscon_init(e2kms);
/* lmscon_init(e2kms); */
sic_init(e2kms);
e2kms->bus = iohub_init(TYPE_IOHUB_PCI_HOST_BRIDGE, TYPE_IOHUB_PCI_DEVICE,
&e2kms->iohub,
rom_memory, get_system_io());
pci_init(e2kms);
}
static void e2k_machine_class_init(ObjectClass *oc, void *data)
@ -278,7 +305,7 @@ static void e2k_machine_class_init(ObjectClass *oc, void *data)
static const TypeInfo e2k_machine_info = {
.name = TYPE_E2K_MACHINE,
.parent = TYPE_MACHINE,
.class_size = sizeof(E2KMachineClass),
.instance_size = sizeof(E2KMachineState),
.class_init = e2k_machine_class_init,
};

3
hw/intc/apic_common.c
View File

@ -296,7 +296,6 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
{
APICCommonState *s = APIC_COMMON(dev);
APICCommonClass *info;
static DeviceState *vapic;
uint32_t instance_id = s->initial_apic_id;
/* Normally initial APIC ID should be no more than hundreds */
@ -306,6 +305,8 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
info->realize(dev, errp);
#if !defined(TARGET_E2K)
static DeviceState *vapic;
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
!hax_enabled() && current_machine->ram_size >= 1024 * 1024) {

85
hw/pci-host/iohub.c
View File

@ -33,6 +33,7 @@
#include "qapi/visitor.h"
#include "qemu/error-report.h"
#include "qom/object.h"
#include "trace.h"
OBJECT_DECLARE_SIMPLE_TYPE(IOHUBState, IOHUB_PCI_HOST_BRIDGE)
@ -40,38 +41,99 @@ struct IOHUBState {
PCIHostState parent_obj;
};
/* PCI config address are 27-bit in length.
* bit 20-27: bus number
* bit 12-19: devfn
* bit 0-11: device register address
*/
#define IOHUB_CONFIG_ADDR_BUS(addr) (((addr) >> 20) & 0xff)
#define IOHUB_CONFIG_ADDR_DEVFN(addr) (((addr) >> 12) & 0xff)
#define IOHUB_CONFIG_ADDR_REG(addr) (((addr) >> 0) & 0xfff)
#define TO_IOHUB_CONFIG_ADDR(bus, devfn, where) ((((bus) & 0xff) << 20) | (((devfn) & 0xff) << 12) | ((where) & 0xfff))
#define TO_PCI_CONFIG_ADDR(bus, devfn, reg) ((((bus) & 0xff) << 16) | (((devfn) & 0xff) << 8) | (((reg) & 0xff) << 0))
static inline uint32_t
iohub_pci_config_addr(hwaddr addr, uint8_t *bus, uint8_t *devfn, uint16_t *reg)
{
*bus = IOHUB_CONFIG_ADDR_BUS(addr);
*devfn = IOHUB_CONFIG_ADDR_DEVFN(addr);
*reg = IOHUB_CONFIG_ADDR_REG(addr);
return TO_PCI_CONFIG_ADDR(*bus, *devfn, *reg);
}
static uint64_t iohub_pci_config_read(void *opaque, hwaddr addr, unsigned size)
{
uint8_t bus, devfn;
uint16_t reg;
uint64_t val;
hwaddr conf_addr = iohub_pci_config_addr(addr, &bus, &devfn, &reg);
val = pci_data_read(opaque, conf_addr, size);
trace_iohub_pci_config_read(addr, conf_addr, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val);
return val;
}
static void iohub_pci_config_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
{
uint8_t bus, devfn;
uint16_t reg;
hwaddr conf_addr = iohub_pci_config_addr(addr, &bus, &devfn, &reg);
trace_iohub_pci_config_write(addr, conf_addr, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val);
pci_data_write(opaque, conf_addr, val, size);
}
static const MemoryRegionOps iohub_pci_config_ops = {
.read = iohub_pci_config_read,
.write = iohub_pci_config_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
PCIBus *iohub_init(const char *host_type, const char *pci_type,
PCIIOHUBState **piohub_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io)
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io)
{
DeviceState *dev;
SysBusDevice *sb;
PCIDevice *d;
PCIHostState *s;
PCIBus *b;
PCIIOHUBState *f;
MemoryRegion *pci_address_space;
MemoryRegion *pci_address_space, *pci_config_as;
dev = qdev_new(host_type);
s = PCI_HOST_BRIDGE(dev);
sb = SYS_BUS_DEVICE(dev);
pci_address_space = g_malloc(sizeof(*pci_address_space));
memory_region_init_alias(pci_address_space, OBJECT(dev),
"pcimem", address_space_mem, 0, E2K_PCIMEM_SIZE);
memory_region_init_io(pci_address_space, OBJECT(dev), NULL, NULL, "pcimem", E2K_PCIMEM_SIZE);
memory_region_add_subregion(address_space_mem, E2K_PCIMEM_BASE, pci_address_space);
s->bus = b = pci_root_bus_new(dev, NULL,
pci_address_space,
address_space_io,
address_space_io,
0, TYPE_PCI_BUS);
object_property_add_child(qdev_get_machine(), "iohub", OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d = pci_create_simple(b, 0, pci_type);
object_property_add_child(qdev_get_machine(), "iohub", OBJECT(dev));
sysbus_realize_and_unref(sb, &error_fatal);
pci_config_as = g_malloc(sizeof(*pci_config_as));
memory_region_init_io(pci_config_as, OBJECT(dev), &iohub_pci_config_ops, s->bus, "pcicfg", E2K_PCICFG_SIZE);
sysbus_init_mmio(sb, pci_config_as);
sysbus_mmio_map(sb, 0, E2K_PCICFG_BASE);
d = pci_create_simple(b, PCI_DEVFN(1, 0), pci_type);
f = *piohub_state = IOHUB_PCI_DEVICE(d);
f->system_memory = address_space_mem;
f->pci_address_space = pci_address_space;
return b;
}
static void iohub_class_init(ObjectClass *oc, void *data)
@ -128,7 +190,6 @@ static void iohub_pcihost_realize(DeviceState *dev, Error **errp)
static void iohub_pcihost_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(oc);
dc->realize = iohub_pcihost_realize;
dc->fw_name = "pci";

4
hw/pci-host/trace-events
View File

@ -6,6 +6,10 @@ bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address i
# grackle.c
grackle_set_irq(int irq_num, int level) "set_irq num %d level %d"
# iohub.c
iohub_pci_config_write(uint64_t addr, uint64_t confaddr, uint8_t bus, uint8_t slot, uint8_t func, uint16_t reg, uint64_t val) "addr 0x%"PRIx64" 0x%"PRIx64" dev %2x:%2x.%d reg 0x%x val 0x%"PRIx64
iohub_pci_config_read(uint64_t addr, uint64_t confaddr, uint8_t bus, uint8_t slot, uint8_t func, uint16_t reg, uint64_t val) "addr 0x%"PRIx64" 0x%"PRIx64" dev %2x:%2x.%d reg 0x%x val 0x%"PRIx64
# mv64361.c
mv64361_region_map(const char *name, uint64_t poffs, uint64_t size, uint64_t moffs) "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64
mv64361_region_enable(const char *op, int num) "Should %s region %d"

4
include/hw/char/lmscon.h
View File

@ -21,9 +21,9 @@
OBJECT_DECLARE_SIMPLE_TYPE(LMSCONState, LMSCON)
struct LMSCONState {
DeviceState parent;
SysBusDevice parent;
uint64_t baseaddr;
MemoryRegion io;
CharBackend chr;
uint8_t tx;
};

9
include/hw/e2k/e2k.h
View File

@ -198,13 +198,6 @@ typedef struct GSIState {
qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
} GSIState;
struct E2KMachineClass {
/*< private >*/
MachineClass parent;
/*< public >*/
};
struct E2KMachineState {
/*< private >*/
MachineClass parent;
@ -228,7 +221,7 @@ struct E2KMachineState {
#define TYPE_E2K_MACHINE MACHINE_TYPE_NAME("e2k")
OBJECT_DECLARE_TYPE(E2KMachineState, E2KMachineClass, E2K_MACHINE)
OBJECT_DECLARE_SIMPLE_TYPE(E2KMachineState, E2K_MACHINE)
void sic_init(E2KMachineState *ms);

1
target/e2k/cpu.c
View File

@ -291,7 +291,6 @@ static void e2k_cpu_realizefn(DeviceState *dev, Error **errp)
e2k_cpu_register_gdb_regs_for_features(cs);
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
qemu_register_reset(e2k_cpu_machine_reset_cb, cpu);
// if (ms->smp.cpus > 1) {

4
target/e2k/helper.c
View File

@ -417,9 +417,9 @@ void HELPER(debug)(CPUE2KState *env)
#ifndef CONFIG_USER_ONLY
static AddressSpace *get_addressspace_by_addr(target_ulong *addr, CPUState *env, MemTxAttrs attrs)
{
if (addr >= E2K_IO_AREA_BASE && addr < E2K_IO_AREA_BASE + E2K_IO_AREA_SIZE)
if (*addr >= E2K_IO_AREA_BASE && *addr < E2K_IO_AREA_BASE + E2K_IO_AREA_SIZE)
{
addr -= E2K_IO_AREA_BASE;
*addr -= E2K_IO_AREA_BASE;
return &address_space_io;
}