apci: switch evt to memory api
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
parent
afafe4bbe0
commit
b5a7c024d2
49
hw/acpi.c
49
hw/acpi.c
@ -275,7 +275,7 @@ uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar)
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return ar->pm1.evt.sts;
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}
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void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val)
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static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val)
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{
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uint16_t pm1_sts = acpi_pm1_evt_get_sts(ar);
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if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) {
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@ -285,7 +285,7 @@ void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val)
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ar->pm1.evt.sts &= ~val;
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}
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void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val)
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static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val)
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{
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ar->pm1.evt.en = val;
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qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC,
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@ -310,6 +310,51 @@ void acpi_pm1_evt_reset(ACPIREGS *ar)
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qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, 0);
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}
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static uint64_t acpi_pm_evt_read(void *opaque, hwaddr addr, unsigned width)
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{
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ACPIREGS *ar = opaque;
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switch (addr) {
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case 0:
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return acpi_pm1_evt_get_sts(ar);
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case 2:
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return ar->pm1.evt.en;
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default:
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return 0;
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}
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}
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static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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ACPIREGS *ar = opaque;
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switch (addr) {
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case 0:
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acpi_pm1_evt_write_sts(ar, val);
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ar->pm1.evt.update_sci(ar);
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break;
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case 2:
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acpi_pm1_evt_write_en(ar, val);
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ar->pm1.evt.update_sci(ar);
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break;
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}
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}
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static const MemoryRegionOps acpi_pm_evt_ops = {
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.read = acpi_pm_evt_read,
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.write = acpi_pm_evt_write,
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.valid.min_access_size = 2,
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.valid.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
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MemoryRegion *parent)
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{
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ar->pm1.evt.update_sci = update_sci;
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memory_region_init_io(&ar->pm1.evt.io, &acpi_pm_evt_ops, ar, "acpi-evt", 4);
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memory_region_add_subregion(parent, 0, &ar->pm1.evt.io);
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}
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/* ACPI PM_TMR */
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void acpi_pm_tmr_update(ACPIREGS *ar, bool enable)
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{
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@ -91,8 +91,10 @@ struct ACPIPMTimer {
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};
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struct ACPIPM1EVT {
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MemoryRegion io;
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uint16_t sts;
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uint16_t en;
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acpi_update_sci_fn update_sci;
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};
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struct ACPIPM1CNT {
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@ -135,10 +137,10 @@ static inline int64_t acpi_pm_tmr_get_clock(void)
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/* PM1a_EVT: piix and ich9 don't implement PM1b. */
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uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar);
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void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val);
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void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val);
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void acpi_pm1_evt_power_down(ACPIREGS *ar);
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void acpi_pm1_evt_reset(ACPIREGS *ar);
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void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
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MemoryRegion *parent);
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/* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */
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void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent);
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@ -105,17 +105,7 @@ static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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ICH9LPCPMRegs *pm = opaque;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_PM1_STS:
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acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
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pm_update_sci(pm);
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break;
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case ICH9_PMIO_PM1_EN:
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pm->acpi_regs.pm1.evt.en = val;
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pm_update_sci(pm);
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break;
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default:
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pm_ioport_write_fallback(opaque, addr, 2, val);
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break;
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@ -125,16 +115,9 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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ICH9LPCPMRegs *pm = opaque;
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uint32_t val;
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switch (addr & ICH9_PMIO_MASK) {
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case ICH9_PMIO_PM1_STS:
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val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
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break;
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case ICH9_PMIO_PM1_EN:
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val = pm->acpi_regs.pm1.evt.en;
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break;
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default:
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val = pm_ioport_read_fallback(opaque, addr, 2);
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break;
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@ -312,6 +295,7 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
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memory_region_add_subregion(get_system_io(), 0, &pm->io);
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acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
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acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
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acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io);
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acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
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acpi_gpe_blk(&pm->acpi_regs, ICH9_PMIO_GPE0_STS);
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@ -113,22 +113,12 @@ static void pm_tmr_timer(ACPIREGS *ar)
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static void pm_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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PIIX4PMState *s = opaque;
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if (width != 2) {
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PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
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(unsigned)addr, width, (unsigned)val);
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}
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switch(addr) {
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case 0x00:
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acpi_pm1_evt_write_sts(&s->ar, val);
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pm_update_sci(s);
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break;
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case 0x02:
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acpi_pm1_evt_write_en(&s->ar, val);
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pm_update_sci(s);
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break;
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default:
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break;
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}
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@ -138,16 +128,9 @@ static void pm_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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static uint64_t pm_ioport_read(void *opaque, hwaddr addr, unsigned width)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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switch(addr) {
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case 0x00:
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val = acpi_pm1_evt_get_sts(&s->ar);
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break;
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case 0x02:
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val = s->ar.pm1.evt.en;
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break;
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default:
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val = 0;
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break;
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@ -455,6 +438,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
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memory_region_add_subregion(get_system_io(), 0, &s->io);
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acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_cnt_init(&s->ar, &s->io);
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acpi_gpe_init(&s->ar, GPE_LEN);
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@ -199,18 +199,8 @@ static void pm_tmr_timer(ACPIREGS *ar)
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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VT686PMState *s = opaque;
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addr &= 0x0f;
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switch (addr) {
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case 0x00:
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acpi_pm1_evt_write_sts(&s->ar, val);
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pm_update_sci(s);
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break;
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case 0x02:
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acpi_pm1_evt_write_en(&s->ar, val);
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pm_update_sci(s);
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break;
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default:
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break;
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}
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@ -219,17 +209,10 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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VT686PMState *s = opaque;
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uint32_t val;
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addr &= 0x0f;
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switch (addr) {
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case 0x00:
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val = acpi_pm1_evt_get_sts(&s->ar);
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break;
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case 0x02:
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val = s->ar.pm1.evt.en;
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break;
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default:
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val = 0;
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break;
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@ -437,6 +420,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
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memory_region_add_subregion(get_system_io(), 0, &s->io);
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acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
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acpi_pm1_cnt_init(&s->ar, &s->io);
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pm_smbus_init(&s->dev.qdev, &s->smb);
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