target-arm: Fix unsigned VRSHL.s8 and .s16 right shifts by type width
Fix handling of unsigned VRSHL.s8 and .s16 right shifts by the type width. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
parent
0670a7b65b
commit
b6c63b9891
@ -605,7 +605,7 @@ uint64_t HELPER(neon_rshl_s64)(uint64_t valop, uint64_t shiftop)
|
||||
tmp < -(ssize_t)sizeof(src1) * 8) { \
|
||||
dest = 0; \
|
||||
} else if (tmp == -(ssize_t)sizeof(src1) * 8) { \
|
||||
dest = src1 >> (tmp - 1); \
|
||||
dest = src1 >> (-tmp - 1); \
|
||||
} else if (tmp < 0) { \
|
||||
dest = (src1 + (1 << (-1 - tmp))) >> -tmp; \
|
||||
} else { \
|
||||
|
Loading…
Reference in New Issue
Block a user