target/ppc: Style fixes for int_helper.c
Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
This commit is contained in:
David Gibson
parent
c647e3fe3d
commit
b6cb41b22c
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@ -137,7 +137,8 @@ uint64_t helper_divde(CPUPPCState *env, uint64_t rau, uint64_t rbu, uint32_t oe)
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/* if x = 0xab, returns 0xababababababababa */
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#define pattern(x) (((x) & 0xff) * (~(target_ulong)0 / 0xff))
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/* substract 1 from each byte, and with inverse, check if MSB is set at each
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/*
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* subtract 1 from each byte, and with inverse, check if MSB is set at each
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* byte.
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* i.e. ((0x00 - 0x01) & ~(0x00)) & 0x80
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* (0xFF & 0xFF) & 0x80 = 0x80 (zero found)
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@ -156,7 +157,8 @@ uint32_t helper_cmpeqb(target_ulong ra, target_ulong rb)
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#undef haszero
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#undef hasvalue
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/* Return invalid random number.
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/*
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* Return invalid random number.
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*
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* FIXME: Add rng backend or other mechanism to get cryptographically suitable
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* random number
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@ -181,7 +183,7 @@ uint64_t helper_bpermd(uint64_t rs, uint64_t rb)
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uint64_t ra = 0;
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for (i = 0; i < 8; i++) {
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int index = (rs >> (i*8)) & 0xFF;
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int index = (rs >> (i * 8)) & 0xFF;
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if (index < 64) {
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if (rb & PPC_BIT(index)) {
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ra |= 1 << i;
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@ -370,7 +372,8 @@ target_ulong helper_divso(CPUPPCState *env, target_ulong arg1,
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/* 602 specific instructions */
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/* mfrom is the most crazy instruction ever seen, imho ! */
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/* Real implementation uses a ROM table. Do the same */
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/* Extremely decomposed:
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/*
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* Extremely decomposed:
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* -arg / 256
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* return 256 * log10(10 + 1.0) + 0.5
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*/
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@ -393,7 +396,7 @@ target_ulong helper_602_mfrom(target_ulong arg)
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for (index = 0; index < ARRAY_SIZE(r->element); index++)
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#else
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#define VECTOR_FOR_INORDER_I(index, element) \
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for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
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for (index = ARRAY_SIZE(r->element) - 1; index >= 0; index--)
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#endif
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/* Saturating arithmetic helpers. */
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@ -634,7 +637,8 @@ void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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} \
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}
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/* VABSDU - Vector absolute difference unsigned
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/*
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* VABSDU - Vector absolute difference unsigned
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* name - instruction mnemonic suffix (b: byte, h: halfword, w: word)
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* element - element type to access from vector
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*/
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@ -739,7 +743,8 @@ void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
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} \
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}
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/* VCMPNEZ - Vector compare not equal to zero
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/*
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* VCMPNEZ - Vector compare not equal to zero
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* suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
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* element - element type to access from vector
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*/
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@ -1138,7 +1143,7 @@ void helper_vpermr(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
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#define VBPERMQ_DW(index) (((index) & 0x40) != 0)
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#define EXTRACT_BIT(avr, i, index) (extract64((avr)->u64[i], index, 1))
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#else
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#define VBPERMQ_INDEX(avr, i) ((avr)->u8[15-(i)])
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#define VBPERMQ_INDEX(avr, i) ((avr)->u8[15 - (i)])
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#define VBPERMD_INDEX(i) (1 - i)
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#define VBPERMQ_DW(index) (((index) & 0x40) == 0)
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#define EXTRACT_BIT(avr, i, index) \
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@ -1169,7 +1174,7 @@ void helper_vbpermq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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int index = VBPERMQ_INDEX(b, i);
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if (index < 128) {
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uint64_t mask = (1ull << (63-(index & 0x3F)));
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uint64_t mask = (1ull << (63 - (index & 0x3F)));
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if (a->u64[VBPERMQ_DW(index)] & mask) {
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perm |= (0x8000 >> i);
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}
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@ -1449,9 +1454,9 @@ void helper_vgbbd(ppc_avr_t *r, ppc_avr_t *b)
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VECTOR_FOR_INORDER_I(i, u8) {
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#if defined(HOST_WORDS_BIGENDIAN)
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t[i>>3] |= VGBBD_MASKS[b->u8[i]] >> (i & 7);
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t[i >> 3] |= VGBBD_MASKS[b->u8[i]] >> (i & 7);
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#else
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t[i>>3] |= VGBBD_MASKS[b->u8[i]] >> (7-(i & 7));
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t[i >> 3] |= VGBBD_MASKS[b->u8[i]] >> (7 - (i & 7));
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#endif
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}
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@ -1463,19 +1468,19 @@ void helper_vgbbd(ppc_avr_t *r, ppc_avr_t *b)
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void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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{ \
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int i, j; \
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trgtyp prod[sizeof(ppc_avr_t)/sizeof(a->srcfld[0])]; \
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trgtyp prod[sizeof(ppc_avr_t) / sizeof(a->srcfld[0])]; \
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\
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VECTOR_FOR_INORDER_I(i, srcfld) { \
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prod[i] = 0; \
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for (j = 0; j < sizeof(a->srcfld[0]) * 8; j++) { \
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if (a->srcfld[i] & (1ull<<j)) { \
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if (a->srcfld[i] & (1ull << j)) { \
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prod[i] ^= ((trgtyp)b->srcfld[i] << j); \
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} \
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} \
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} \
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\
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VECTOR_FOR_INORDER_I(i, trgfld) { \
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r->trgfld[i] = prod[2*i] ^ prod[2*i+1]; \
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r->trgfld[i] = prod[2 * i] ^ prod[2 * i + 1]; \
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} \
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}
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@ -1493,7 +1498,7 @@ void helper_vpmsumd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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VECTOR_FOR_INORDER_I(i, u64) {
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prod[i] = 0;
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for (j = 0; j < 64; j++) {
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if (a->u64[i] & (1ull<<j)) {
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if (a->u64[i] & (1ull << j)) {
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prod[i] ^= (((__uint128_t)b->u64[i]) << j);
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}
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}
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@ -1508,7 +1513,7 @@ void helper_vpmsumd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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VECTOR_FOR_INORDER_I(i, u64) {
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prod[i].VsrD(1) = prod[i].VsrD(0) = 0;
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for (j = 0; j < 64; j++) {
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if (a->u64[i] & (1ull<<j)) {
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if (a->u64[i] & (1ull << j)) {
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ppc_avr_t bshift;
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if (j == 0) {
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bshift.VsrD(0) = 0;
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@ -1548,9 +1553,9 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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VECTOR_FOR_INORDER_I(j, u32) {
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uint32_t e = x[i]->u32[j];
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result.u16[4*i+j] = (((e >> 9) & 0xfc00) |
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((e >> 6) & 0x3e0) |
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((e >> 3) & 0x1f));
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result.u16[4 * i + j] = (((e >> 9) & 0xfc00) |
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((e >> 6) & 0x3e0) |
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((e >> 3) & 0x1f));
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}
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}
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*r = result;
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@ -1568,7 +1573,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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\
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VECTOR_FOR_INORDER_I(i, from) { \
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result.to[i] = cvt(a0->from[i], &sat); \
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result.to[i+ARRAY_SIZE(r->from)] = cvt(a1->from[i], &sat); \
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result.to[i + ARRAY_SIZE(r->from)] = cvt(a1->from[i], &sat);\
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} \
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*r = result; \
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if (dosat && sat) { \
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@ -1736,9 +1741,11 @@ VEXTU_X_DO(vextuhrx, 16, 0)
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VEXTU_X_DO(vextuwrx, 32, 0)
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#undef VEXTU_X_DO
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/* The specification says that the results are undefined if all of the
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* shift counts are not identical. We check to make sure that they are
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* to conform to what real hardware appears to do. */
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/*
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* The specification says that the results are undefined if all of the
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* shift counts are not identical. We check to make sure that they
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* are to conform to what real hardware appears to do.
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*/
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#define VSHIFT(suffix, leftp) \
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void helper_vs##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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{ \
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@ -1805,9 +1812,10 @@ void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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int i;
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unsigned int shift, bytes;
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/* Use reverse order, as destination and source register can be same. Its
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* being modified in place saving temporary, reverse order will guarantee
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* that computed result is not fed back.
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/*
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* Use reverse order, as destination and source register can be
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* same. Its being modified in place saving temporary, reverse
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* order will guarantee that computed result is not fed back.
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*/
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for (i = ARRAY_SIZE(r->u8) - 1; i >= 0; i--) {
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shift = b->u8[i] & 0x7; /* extract shift value */
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@ -1840,7 +1848,7 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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#if defined(HOST_WORDS_BIGENDIAN)
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memmove(&r->u8[0], &a->u8[sh], 16 - sh);
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memset(&r->u8[16-sh], 0, sh);
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memset(&r->u8[16 - sh], 0, sh);
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#else
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memmove(&r->u8[sh], &a->u8[0], 16 - sh);
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memset(&r->u8[0], 0, sh);
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@ -2112,7 +2120,7 @@ void helper_vsum4ubs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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ppc_avr_t result; \
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\
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for (i = 0; i < ARRAY_SIZE(r->u32); i++) { \
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uint16_t e = b->u16[hi ? i : i+4]; \
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uint16_t e = b->u16[hi ? i : i + 4]; \
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uint8_t a = (e >> 15) ? 0xff : 0; \
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uint8_t r = (e >> 10) & 0x1f; \
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uint8_t g = (e >> 5) & 0x1f; \
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@ -2463,7 +2471,7 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n)
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{
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if (n & 1) {
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bcd->u8[BCD_DIG_BYTE(n)] &= 0x0F;
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bcd->u8[BCD_DIG_BYTE(n)] |= (digit<<4);
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bcd->u8[BCD_DIG_BYTE(n)] |= (digit << 4);
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} else {
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bcd->u8[BCD_DIG_BYTE(n)] &= 0xF0;
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bcd->u8[BCD_DIG_BYTE(n)] |= digit;
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@ -3220,7 +3228,7 @@ void helper_vshasigmad(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six)
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for (i = 0; i < ARRAY_SIZE(r->u64); i++) {
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if (st == 0) {
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if ((six & (0x8 >> (2*i))) == 0) {
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if ((six & (0x8 >> (2 * i))) == 0) {
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r->VsrD(i) = ror64(a->VsrD(i), 1) ^
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ror64(a->VsrD(i), 8) ^
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(a->VsrD(i) >> 7);
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@ -3230,7 +3238,7 @@ void helper_vshasigmad(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six)
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(a->VsrD(i) >> 6);
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}
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} else { /* st == 1 */
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if ((six & (0x8 >> (2*i))) == 0) {
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if ((six & (0x8 >> (2 * i))) == 0) {
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r->VsrD(i) = ror64(a->VsrD(i), 28) ^
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ror64(a->VsrD(i), 34) ^
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ror64(a->VsrD(i), 39);
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