tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
The movcond opcode is now mandatory for backends to implement. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
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@ -100,7 +100,7 @@ DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
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DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32))
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DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32))
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DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
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DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
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DEF(neg_i32, 1, 1, 0, 0)
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DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
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DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
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DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
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@ -171,7 +171,7 @@ DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
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DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
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DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
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DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
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DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
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DEF(neg_i64, 1, 1, 0, IMPL64)
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DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
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DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
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DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
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@ -82,7 +82,6 @@ typedef uint64_t TCGRegSet;
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#define TCG_TARGET_HAS_bswap16_i64 0
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#define TCG_TARGET_HAS_bswap32_i64 0
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#define TCG_TARGET_HAS_bswap64_i64 0
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#define TCG_TARGET_HAS_neg_i64 0
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#define TCG_TARGET_HAS_not_i64 0
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#define TCG_TARGET_HAS_andc_i64 0
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#define TCG_TARGET_HAS_orc_i64 0
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@ -71,7 +71,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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@ -107,7 +106,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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@ -101,7 +101,6 @@ extern bool use_neon_instructions;
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 0
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@ -135,7 +135,6 @@ typedef enum {
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_andc_i32 have_bmi1
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#define TCG_TARGET_HAS_orc_i32 0
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@ -171,7 +170,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_andc_i64 have_bmi1
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#define TCG_TARGET_HAS_orc_i64 0
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@ -119,7 +119,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 0
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@ -153,7 +152,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 0
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@ -184,12 +184,10 @@ extern bool use_mips32r2_instructions;
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#endif
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
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#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
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#define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
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#endif
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@ -2001,11 +2001,11 @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op)
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switch (ctx->type) {
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case TCG_TYPE_I32:
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neg_op = INDEX_op_neg_i32;
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have_neg = TCG_TARGET_HAS_neg_i32;
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have_neg = true;
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break;
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case TCG_TYPE_I64:
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neg_op = INDEX_op_neg_i64;
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have_neg = TCG_TARGET_HAS_neg_i64;
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have_neg = true;
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break;
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case TCG_TYPE_V64:
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case TCG_TYPE_V128:
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@ -83,7 +83,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_eqv_i32 1
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@ -120,7 +119,6 @@ typedef enum {
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 1
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@ -109,7 +109,6 @@ extern bool have_zbb;
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#define TCG_TARGET_HAS_bswap16_i32 have_zbb
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#define TCG_TARGET_HAS_bswap32_i32 have_zbb
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_andc_i32 have_zbb
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#define TCG_TARGET_HAS_orc_i32 have_zbb
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#define TCG_TARGET_HAS_eqv_i32 have_zbb
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@ -142,7 +141,6 @@ extern bool have_zbb;
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#define TCG_TARGET_HAS_bswap32_i64 have_zbb
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#define TCG_TARGET_HAS_bswap64_i64 have_zbb
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_andc_i64 have_zbb
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#define TCG_TARGET_HAS_orc_i64 have_zbb
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#define TCG_TARGET_HAS_eqv_i64 have_zbb
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@ -82,7 +82,6 @@ extern uint64_t s390_facilities[3];
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3)
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_andc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
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#define TCG_TARGET_HAS_orc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
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#define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3)
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@ -117,7 +116,6 @@ extern uint64_t s390_facilities[3];
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3)
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_andc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
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#define TCG_TARGET_HAS_orc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
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#define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3)
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@ -91,7 +91,6 @@ extern bool use_vis3_instructions;
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#define TCG_TARGET_HAS_ext16u_i32 0
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#define TCG_TARGET_HAS_bswap16_i32 0
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#define TCG_TARGET_HAS_bswap32_i32 0
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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@ -127,7 +126,6 @@ extern bool use_vis3_instructions;
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#define TCG_TARGET_HAS_bswap16_i64 0
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#define TCG_TARGET_HAS_bswap32_i64 0
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#define TCG_TARGET_HAS_bswap64_i64 0
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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22
tcg/tcg-op.c
22
tcg/tcg-op.c
@ -363,9 +363,8 @@ void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
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{
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if (arg1 == 0 && TCG_TARGET_HAS_neg_i32) {
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/* Don't recurse with tcg_gen_neg_i32. */
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tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2);
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if (arg1 == 0) {
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tcg_gen_neg_i32(ret, arg2);
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} else {
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tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2);
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}
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@ -383,11 +382,7 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
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void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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if (TCG_TARGET_HAS_neg_i32) {
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tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
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} else {
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tcg_gen_subfi_i32(ret, 0, arg);
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}
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tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
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}
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void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
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@ -1744,9 +1739,8 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
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void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
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{
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if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) {
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/* Don't recurse with tcg_gen_neg_i64. */
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tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2);
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if (arg1 == 0) {
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tcg_gen_neg_i64(ret, arg2);
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} else if (TCG_TARGET_REG_BITS == 64) {
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tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2);
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} else {
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@ -1772,10 +1766,12 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
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void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
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{
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if (TCG_TARGET_HAS_neg_i64) {
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
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} else {
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tcg_gen_subfi_i64(ret, 0, arg);
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TCGv_i32 zero = tcg_constant_i32(0);
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tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
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zero, zero, TCGV_LOW(arg), TCGV_HIGH(arg));
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}
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}
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@ -1988,6 +1988,7 @@ bool tcg_op_supported(TCGOpcode op)
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case INDEX_op_st_i32:
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case INDEX_op_add_i32:
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case INDEX_op_sub_i32:
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case INDEX_op_neg_i32:
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case INDEX_op_mul_i32:
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case INDEX_op_and_i32:
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case INDEX_op_or_i32:
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@ -2045,8 +2046,6 @@ bool tcg_op_supported(TCGOpcode op)
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return TCG_TARGET_HAS_bswap32_i32;
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case INDEX_op_not_i32:
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return TCG_TARGET_HAS_not_i32;
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case INDEX_op_neg_i32:
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return TCG_TARGET_HAS_neg_i32;
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case INDEX_op_andc_i32:
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return TCG_TARGET_HAS_andc_i32;
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case INDEX_op_orc_i32:
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@ -2085,6 +2084,7 @@ bool tcg_op_supported(TCGOpcode op)
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case INDEX_op_st_i64:
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case INDEX_op_add_i64:
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case INDEX_op_sub_i64:
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case INDEX_op_neg_i64:
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case INDEX_op_mul_i64:
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case INDEX_op_and_i64:
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case INDEX_op_or_i64:
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@ -2141,8 +2141,6 @@ bool tcg_op_supported(TCGOpcode op)
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return TCG_TARGET_HAS_bswap64_i64;
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case INDEX_op_not_i64:
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return TCG_TARGET_HAS_not_i64;
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case INDEX_op_neg_i64:
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return TCG_TARGET_HAS_neg_i64;
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case INDEX_op_andc_i64:
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return TCG_TARGET_HAS_andc_i64;
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case INDEX_op_orc_i64:
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@ -733,12 +733,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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regs[r0] = ~regs[r1];
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break;
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#endif
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#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
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CASE_32_64(neg)
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tci_args_rr(insn, &r0, &r1);
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regs[r0] = -regs[r1];
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break;
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#endif
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#if TCG_TARGET_REG_BITS == 64
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/* Load/store operations (64 bit). */
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@ -65,7 +65,6 @@
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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@ -99,7 +98,6 @@
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#define TCG_TARGET_HAS_clz_i64 1
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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