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target/nios2: Rewrite interrupt handling

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Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts
are disabled at a particular point in time, instead queuing the value
into cpu->irq_pending.  This is more complicated than required.

Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt,
and exclusively check for interrupts disabled in nios2_cpu_exec_interrupt.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-02-26 01:56:15 -10:00
parent 8d8d73b551
commit b72c9d5951
5 changed files with 9 additions and 36 deletions
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10
target/nios2/cpu.c
View File

@ -73,12 +73,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level)
env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
env->irq_pending = 0;
if (env->regs[CR_IPENDING]) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else if (!env->irq_pending) {
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
@ -134,7 +131,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
CPUNios2State *env = &cpu->env;
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
(env->regs[CR_STATUS] & CR_STATUS_PIE)) {
(env->regs[CR_STATUS] & CR_STATUS_PIE) &&
(env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) {
cs->exception_index = EXCP_IRQ;
nios2_cpu_do_interrupt(cs);
return true;

1
target/nios2/cpu.h
View File

@ -160,7 +160,6 @@ struct CPUNios2State {
#if !defined(CONFIG_USER_ONLY)
Nios2MMU mmu;
uint32_t irq_pending;
#endif
int error_code;
};

1
target/nios2/helper.h
View File

@ -24,5 +24,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
DEF_HELPER_1(check_interrupts, void, env)
#endif

19
target/nios2/op_helper.c
View File

@ -21,28 +21,9 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
#include "qemu/main-loop.h"
#if !defined(CONFIG_USER_ONLY)
static void nios2_check_interrupts(CPUNios2State *env)
{
if (env->irq_pending &&
(env->regs[CR_STATUS] & CR_STATUS_PIE)) {
env->irq_pending = 0;
cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
}
}
void helper_check_interrupts(CPUNios2State *env)
{
qemu_mutex_lock_iothread();
nios2_check_interrupts(env);
qemu_mutex_unlock_iothread();
}
#endif /* !CONFIG_USER_ONLY */
void helper_raise_exception(CPUNios2State *env, uint32_t index)
{
CPUState *cs = env_cpu(env);

14
target/nios2/translate.c
View File

@ -491,19 +491,15 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
case CR_IPENDING:
/* ipending is read only, writes ignored. */
break;
case CR_STATUS:
case CR_IENABLE:
/* If interrupts were enabled using WRCTL, trigger them. */
dc->base.is_jmp = DISAS_UPDATE;
/* fall through */
default:
tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
break;
}
/* If interrupts were enabled using WRCTL, trigger them. */
if ((instr.imm5 + CR_BASE) == CR_STATUS) {
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_check_interrupts(cpu_env);
dc->base.is_jmp = DISAS_UPDATE;
}
#endif
}