target/arm: Split out arm_env_mmu_index
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -7841,7 +7841,7 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
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uint64_t vaddr_in = (uint64_t) value;
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uint64_t vaddr = vaddr_in & ~(dline_size - 1);
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void *haddr;
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int mem_idx = cpu_mmu_index(env, false);
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int mem_idx = arm_env_mmu_index(env);
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/* This won't be crossing page boundaries */
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haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
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@ -40,6 +40,11 @@
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#define BANK_HYP 6
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#define BANK_MON 7
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static inline int arm_env_mmu_index(CPUARMState *env)
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{
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return EX_TBFLAG_ANY(env->hflags, MMUIDX);
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}
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static inline bool excp_is_internal(int excp)
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{
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/* Return true if this exception number represents a QEMU-internal
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@ -856,7 +856,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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tbii = EX_TBFLAG_A64(env->hflags, TBII);
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if ((tbii >> extract64(new_pc, 55, 1)) & 1) {
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/* TBI is enabled. */
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int core_mmu_idx = cpu_mmu_index(env, false);
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int core_mmu_idx = arm_env_mmu_index(env);
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if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) {
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new_pc = sextract64(new_pc, 0, 56);
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} else {
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@ -925,7 +925,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
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*/
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int blocklen = 4 << env_archcpu(env)->dcz_blocksize;
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uint64_t vaddr = vaddr_in & ~(blocklen - 1);
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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void *mem;
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/*
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@ -291,7 +291,7 @@ static int load_tag1(uint64_t ptr, uint8_t *mem)
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uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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uint8_t *mem;
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int rtag = 0;
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@ -311,7 +311,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra)
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{
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if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) {
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arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE,
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cpu_mmu_index(env, false), ra);
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arm_env_mmu_index(env), ra);
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g_assert_not_reached();
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}
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}
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@ -344,7 +344,7 @@ typedef void stg_store1(uint64_t, uint8_t *, int);
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static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt,
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uintptr_t ra, stg_store1 store1)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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uint8_t *mem;
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check_tag_aligned(env, ptr, ra);
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@ -371,7 +371,7 @@ void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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uintptr_t ra = GETPC();
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check_tag_aligned(env, ptr, ra);
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@ -381,7 +381,7 @@ void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)
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static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,
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uintptr_t ra, stg_store1 store1)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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int tag = allocation_tag_from_addr(xt);
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uint8_t *mem1, *mem2;
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@ -429,7 +429,7 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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uintptr_t ra = GETPC();
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int in_page = -(ptr | TARGET_PAGE_MASK);
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@ -445,7 +445,7 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
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uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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uintptr_t ra = GETPC();
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int gm_bs = env_archcpu(env)->gm_blocksize;
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int gm_bs_bytes = 4 << gm_bs;
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@ -505,7 +505,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
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void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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uintptr_t ra = GETPC();
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int gm_bs = env_archcpu(env)->gm_blocksize;
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int gm_bs_bytes = 4 << gm_bs;
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@ -555,7 +555,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
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void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
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{
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uintptr_t ra = GETPC();
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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int log2_dcz_bytes, log2_tag_bytes;
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intptr_t dcz_bytes, tag_bytes;
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uint8_t *mem;
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@ -5481,7 +5481,7 @@ bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault,
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CPUARMState *env, target_ulong addr,
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MMUAccessType access_type, uintptr_t retaddr)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int mmu_idx = arm_env_mmu_index(env);
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int mem_off = info->mem_off_first[0];
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bool nofault = fault == FAULT_NO;
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bool have_work = true;
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@ -6529,7 +6529,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
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sve_ldst1_host_fn *host_fn,
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sve_ldst1_tlb_fn *tlb_fn)
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{
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const int mmu_idx = cpu_mmu_index(env, false);
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const int mmu_idx = arm_env_mmu_index(env);
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const intptr_t reg_max = simd_oprsz(desc);
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const int scale = simd_data(desc);
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ARMVectorReg scratch;
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@ -6715,7 +6715,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
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sve_ldst1_host_fn *host_fn,
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sve_ldst1_tlb_fn *tlb_fn)
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{
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const int mmu_idx = cpu_mmu_index(env, false);
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const int mmu_idx = arm_env_mmu_index(env);
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const intptr_t reg_max = simd_oprsz(desc);
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const int scale = simd_data(desc);
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const int esize = 1 << esz;
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@ -6920,7 +6920,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm,
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sve_ldst1_host_fn *host_fn,
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sve_ldst1_tlb_fn *tlb_fn)
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{
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const int mmu_idx = cpu_mmu_index(env, false);
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const int mmu_idx = arm_env_mmu_index(env);
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const intptr_t reg_max = simd_oprsz(desc);
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const int scale = simd_data(desc);
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void *host[ARM_MAX_VQ * 4];
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@ -281,7 +281,7 @@ void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
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{
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ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
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int target_el = exception_target_el(env);
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int mmu_idx = cpu_mmu_index(env, true);
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int mmu_idx = arm_env_mmu_index(env);
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uint32_t fsc;
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env->exception.vaddress = pc;
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