ppc: Add real mode CI load/store instructions for P7 and P8
Those instructions are only available in hypervisor real mode and allow cache inhibited garded access to devices in that mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Benjamin Herrenschmidt
David Gibson
parent
9b2fadda3e
commit
b781537560
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@ -1912,6 +1912,8 @@ enum {
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PPC_POPCNTB = 0x0000000000001000ULL,
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/* string load / store */
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PPC_STRING = 0x0000000000002000ULL,
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/* real mode cache inhibited load / store */
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PPC_CILDST = 0x0000000000004000ULL,
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/* Floating-point unit extensions */
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/* Optional floating point instructions */
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@ -2026,7 +2028,7 @@ enum {
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| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
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| PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
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| PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
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| PPC_POPCNTWD)
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| PPC_POPCNTWD | PPC_CILDST)
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/* extended type values */
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@ -193,7 +193,7 @@ struct DisasContext {
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uint32_t opcode;
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uint32_t exception;
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/* Routine used to access memory */
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bool pr, hv;
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bool pr, hv, dr;
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bool lazy_tlb_flush;
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int mem_idx;
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int access_type;
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@ -388,6 +388,7 @@ typedef struct opcode_t {
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#if defined(CONFIG_USER_ONLY)
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#define CHK_HV GEN_PRIV
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#define CHK_SV GEN_PRIV
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#define CHK_HVRM GEN_PRIV
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#else
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#define CHK_HV \
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do { \
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@ -401,6 +402,12 @@ typedef struct opcode_t {
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GEN_PRIV; \
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} \
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} while (0)
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#define CHK_HVRM \
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do { \
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if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
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GEN_PRIV; \
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} \
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} while (0)
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#endif
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#define CHK_NONE
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@ -2927,18 +2934,23 @@ static void glue(gen_, name##ux)(DisasContext *ctx)
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tcg_temp_free(EA); \
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}
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#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
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#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
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static void glue(gen_, name##x)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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chk; \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
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tcg_temp_free(EA); \
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}
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#define GEN_LDX(name, ldop, opc2, opc3, type) \
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GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
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GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
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#define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
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GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
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#define GEN_LDS(name, ldop, op, type) \
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GEN_LD(name, ldop, op | 0x20, type); \
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@ -2964,6 +2976,12 @@ GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
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/* ldx */
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GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
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/* CI load/store variants */
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GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
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GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
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GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
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GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
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static void gen_ld(DisasContext *ctx)
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{
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TCGv EA;
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@ -3082,10 +3100,11 @@ static void glue(gen_, name##ux)(DisasContext *ctx)
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tcg_temp_free(EA); \
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}
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#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
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#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
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static void glue(gen_, name##x)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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chk; \
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gen_set_access_type(ctx, ACCESS_INT); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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@ -3093,7 +3112,10 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
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tcg_temp_free(EA); \
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}
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#define GEN_STX(name, stop, opc2, opc3, type) \
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GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
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GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
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#define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
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GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
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#define GEN_STS(name, stop, op, type) \
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GEN_ST(name, stop, op | 0x20, type); \
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@ -3110,6 +3132,10 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER);
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#if defined(TARGET_PPC64)
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GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
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GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
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GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
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GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
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GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
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GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
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static void gen_std(DisasContext *ctx)
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{
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@ -3198,7 +3224,7 @@ static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
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TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
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GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
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#endif /* TARGET_PPC64 */
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/* sthbrx */
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@ -3224,7 +3250,7 @@ static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
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TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
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tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
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GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
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#endif /* TARGET_PPC64 */
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/*** Integer load and store multiple ***/
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@ -10238,7 +10264,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
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GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_LDUX(name, ldop, opc2, opc3, type) \
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GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
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#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
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#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
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GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
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#define GEN_LDS(name, ldop, op, type) \
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GEN_LD(name, ldop, op | 0x20, type) \
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@ -10255,7 +10281,13 @@ GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
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GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
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GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
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GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
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GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
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GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
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/* HV/P7 and later only */
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GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
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GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
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GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
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GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
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#endif
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GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
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GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
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@ -10271,7 +10303,7 @@ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
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GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
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#define GEN_STUX(name, stop, opc2, opc3, type) \
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GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
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#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
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#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
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GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
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#define GEN_STS(name, stop, op, type) \
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GEN_ST(name, stop, op | 0x20, type) \
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@ -10285,7 +10317,11 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
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#if defined(TARGET_PPC64)
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GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
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GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
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GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
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GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
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GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
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GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
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GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
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GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
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#endif
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GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
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GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
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@ -11453,6 +11489,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
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ctx.spr_cb = env->spr_cb;
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ctx.pr = msr_pr;
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ctx.mem_idx = env->dmmu_idx;
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ctx.dr = msr_dr;
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#if !defined(CONFIG_USER_ONLY)
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ctx.hv = msr_hv || !env->has_hv_mode;
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#endif
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@ -8404,7 +8404,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
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PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD |
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PPC_CILDST;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
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PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
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@ -8485,7 +8486,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
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PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD |
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PPC_CILDST;
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pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
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PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
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