OpenE2K/qemu-e2k
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* Fix for NULL segments (Bin Meng)

Browse Source 
* Support for 32768 CPUs on x86 without IOMMU (David)
 * PDEP/PEXT fix and testcase (myself)
 * Remove bios_name and ram_size globals (myself)
 * qemu_init rationalization (myself)
 * Update kernel-doc (myself + upstream patches)
 * Propagate MemTxResult across DMA and PCI functions (Philippe)
 * Remove master/slave when applicable (Philippe)
 * WHPX support for in-kernel irqchip (Sunil)
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAl/SWS4UHHBib256aW5p
 QHJlZGhhdC5jb20ACgkQv/vSX3jHroMHLAf8Cr1nOn1ou2S2H9vePeoqRAVGdQBv
 tbQ/nZs+2NZMyhLF7mBj7y6Ym0wNyXzkyiFnN1wR04V5e0tF+q1Y0OOZtihJ+Ntk
 esjzHAzdqS22xI2dNnNDBo69eQQKDq3C0Ug5x6z63tO81AoTNKP+vq+QbZqe7v7K
 2TScroAnhX9zE5Hz1+qJ35w13EMCNFnUPHNcOwxVSGHj4HNoEpIjjcE6rme46jX+
 REsEGKJKIJ88aV2hzOLSrdJ0/mNuWsjfOvcfgtoIYUPbb55hHMykqD+LapoyEp8K
 gjnco6JT6wWFN1+tVxTjY4TaERVw+NGomd2QyHSbanDoRd8igFhxu2gBnQ==
 =yeQi
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* Fix for NULL segments (Bin Meng)
* Support for 32768 CPUs on x86 without IOMMU (David)
* PDEP/PEXT fix and testcase (myself)
* Remove bios_name and ram_size globals (myself)
* qemu_init rationalization (myself)
* Update kernel-doc (myself + upstream patches)
* Propagate MemTxResult across DMA and PCI functions (Philippe)
* Remove master/slave when applicable (Philippe)
* WHPX support for in-kernel irqchip (Sunil)

# gpg: Signature made Thu 10 Dec 2020 17:21:50 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream: (113 commits)
  scripts: kernel-doc: remove unnecessary change wrt Linux
  Revert "docs: temporarily disable the kernel-doc extension"
  scripts: kernel-doc: use :c:union when needed
  scripts: kernel-doc: split typedef complex regex
  scripts: kernel-doc: fix typedef parsing
  Revert "kernel-doc: Handle function typedefs that return pointers"
  Revert "kernel-doc: Handle function typedefs without asterisks"
  scripts: kernel-doc: try to use c:function if possible
  scripts: kernel-doc: fix line number handling
  scripts: kernel-doc: allow passing desired Sphinx C domain dialect
  scripts: kernel-doc: don't mangle with parameter list
  scripts: kernel-doc: fix typedef identification
  scripts: kernel-doc: reimplement -nofunction argument
  scripts: kernel-doc: fix troubles with line counts
  scripts: kernel-doc: use a less pedantic markup for funcs on Sphinx 3.x
  scripts: kernel-doc: make it more compatible with Sphinx 3.x
  Revert "kernel-doc: Use c:struct for Sphinx 3.0 and later"
  Revert "scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments"
  scripts: kernel-doc: add support for typedef enum
  kernel-doc: add support for ____cacheline_aligned attribute
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-12-11 13:50:35 +00:00
commit b785d25e91
151 changed files with 2883 additions and 1772 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -452,6 +452,7 @@ WHPX CPUs
M: Sunil Muthuswamy <sunilmut@microsoft.com>
S: Supported
F: target/i386/whpx-all.c
F: target/i386/whpx-apic.c
F: target/i386/whpx-cpus.c
F: target/i386/whp-dispatch.h
F: accel/stubs/whpx-stub.c

2
docs/devel/loads-stores.rst
View File

@ -483,6 +483,8 @@ make sure our existing code is doing things correctly.
Regexes for git grep
- ``\<dma_memory_\(read\|write\|rw\)\>``
- ``\<ldu\?[bwlq]\(_[bl]e\)\?_dma\>``
- ``\<st[bwlq]\(_[bl]e\)\?_dma\>``
``pci_dma_*`` and ``{ld,st}*_pci_dma``
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

2
docs/specs/tpm.rst
View File

@ -343,7 +343,7 @@ In case an Arm virt machine is emulated, use the following command line:
-device tpm-tis-device,tpmdev=tpm0 \
-device virtio-blk-pci,drive=drv0 \
-drive format=qcow2,file=hda.qcow2,if=none,id=drv0 \
-drive if=pflash,format=raw,file=flash0.img,readonly \
-drive if=pflash,format=raw,file=flash0.img,readonly=on \
-drive if=pflash,format=raw,file=flash1.img
In case SeaBIOS is used as firmware, it should show the TPM menu item

6
docs/sphinx/kerneldoc.py
View File

@ -69,6 +69,11 @@ class KernelDocDirective(Directive):
env = self.state.document.settings.env
cmd = env.config.kerneldoc_bin + ['-rst', '-enable-lineno']
# Pass the version string to kernel-doc, as it needs to use a different
# dialect, depending what the C domain supports for each specific
# Sphinx versions
cmd += ['-sphinx-version', sphinx.__version__]
filename = env.config.kerneldoc_srctree + '/' + self.arguments[0]
export_file_patterns = []
@ -99,7 +104,6 @@ class KernelDocDirective(Directive):
env.note_dependency(os.path.abspath(f))
cmd += ['-export-file', f]
cmd += ['-sphinx-version', sphinx.__version__]
cmd += [filename]
try:

3
hw/alpha/dp264.c
View File

@ -21,6 +21,7 @@
#include "hw/dma/i8257.h"
#include "net/net.h"
#include "qemu/cutils.h"
#include "qemu/datadir.h"
#include "net/net.h"
#define MAX_IDE_BUS 2
@ -107,7 +108,7 @@ static void clipper_init(MachineState *machine)
but one explicitly written for the emulation, we might as
well load it directly from and ELF image. */
palcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
bios_name ? bios_name : "palcode-clipper");
machine->firmware ?: "palcode-clipper");
if (palcode_filename == NULL) {
error_report("no palcode provided");
exit(1);

8
hw/arm/aspeed.c
View File

@ -309,7 +309,7 @@ static void aspeed_machine_init(MachineState *machine)
/*
* This will error out if isize is not supported by memory controller.
*/
object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size,
object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
&error_fatal);
for (i = 0; i < sc->macs_num; i++) {
@ -346,8 +346,8 @@ static void aspeed_machine_init(MachineState *machine)
max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
&error_abort);
memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
"max_ram", max_ram_size - ram_size);
memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram);
"max_ram", max_ram_size - machine->ram_size);
memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
bmc->fmc_model : amc->fmc_model);
@ -392,7 +392,7 @@ static void aspeed_machine_init(MachineState *machine)
aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
}
aspeed_board_binfo.ram_size = ram_size;
aspeed_board_binfo.ram_size = machine->ram_size;
aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
aspeed_board_binfo.nb_cpus = sc->num_cpus;

1
hw/arm/boot.c
View File

@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include <libfdt.h>

2
hw/arm/cubieboard.c
View File

@ -40,7 +40,7 @@ static void cubieboard_init(MachineState *machine)
DeviceState *carddev;
/* BIOS is not supported by this board */
if (bios_name) {
if (machine->firmware) {
error_report("BIOS not supported for this machine");
exit(1);
}

20
hw/arm/digic_boards.c
View File

@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/boards.h"
#include "exec/address-spaces.h"
@ -70,19 +71,20 @@ static void digic4_board_init(MachineState *machine, DigicBoard *board)
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
if (board->add_rom0) {
board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);
board->add_rom0(s, DIGIC4_ROM0_BASE,
machine->firmware ?: board->rom0_def_filename);
}
if (board->add_rom1) {
board->add_rom1(s, DIGIC4_ROM1_BASE, board->rom1_def_filename);
board->add_rom1(s, DIGIC4_ROM1_BASE,
machine->firmware ?: board->rom1_def_filename);
}
}
static void digic_load_rom(DigicState *s, hwaddr addr,
hwaddr max_size, const char *def_filename)
hwaddr max_size, const char *filename)
{
target_long rom_size;
const char *filename;
if (qtest_enabled()) {
/* qtest runs no code so don't attempt a ROM load which
@ -91,12 +93,6 @@ static void digic_load_rom(DigicState *s, hwaddr addr,
return;
}
if (bios_name) {
filename = bios_name;
} else {
filename = def_filename;
}
if (filename) {
char *fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename);
@ -119,7 +115,7 @@ static void digic_load_rom(DigicState *s, hwaddr addr,
* 64M Bit (4Mx16) Page Mode / Multi-Bank NOR Flash Memory
*/
static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr,
const char *def_filename)
const char *filename)
{
#define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024)
#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024)
@ -131,7 +127,7 @@ static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr,
0x00EC, 0x007E, 0x0003, 0x0001,
0x0555, 0x2aa, 0);
digic_load_rom(s, addr, FLASH_K8P3215UQB_SIZE, def_filename);
digic_load_rom(s, addr, FLASH_K8P3215UQB_SIZE, filename);
}
static DigicBoard digic4_board_canon_a1100 = {

9
hw/arm/highbank.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
@ -297,16 +298,16 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
&error_fatal);
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
if (bios_name != NULL) {
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (machine->firmware != NULL) {
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (sysboot_filename != NULL) {
if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
error_report("Unable to load %s", bios_name);
error_report("Unable to load %s", machine->firmware);
exit(1);
}
g_free(sysboot_filename);
} else {
error_report("Unable to find %s", bios_name);
error_report("Unable to find %s", machine->firmware);
exit(1);
}
}

6
hw/arm/npcm7xx_boards.c
View File

@ -23,6 +23,7 @@
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "sysemu/sysemu.h"
@ -33,13 +34,10 @@ static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
{
const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
g_autofree char *filename = NULL;
int ret;
if (!bios_name) {
bios_name = npcm7xx_default_bootrom;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (!filename) {
error_report("Could not find ROM image '%s'", bios_name);

2
hw/arm/orangepi.c
View File

@ -41,7 +41,7 @@ static void orangepi_init(MachineState *machine)
DeviceState *carddev;
/* BIOS is not supported by this board */
if (bios_name) {
if (machine->firmware) {
error_report("BIOS not supported for this machine");
exit(1);
}

3
hw/arm/sbsa-ref.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/units.h"
@ -319,6 +320,7 @@ static bool sbsa_firmware_init(SBSAMachineState *sms,
MemoryRegion *sysmem,
MemoryRegion *secure_sysmem)
{
const char *bios_name;
int i;
BlockBackend *pflash_blk0;
@ -332,6 +334,7 @@ static bool sbsa_firmware_init(SBSAMachineState *sms,
pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]);
bios_name = MACHINE(sms)->firmware;
if (bios_name) {
char *fname;
MemoryRegion *mr;

32
hw/arm/spitz.c
View File

@ -578,7 +578,7 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
OBJECT_DECLARE_SIMPLE_TYPE(SpitzLCDTG, SPITZ_LCDTG)
struct SpitzLCDTG {
SSISlave ssidev;
SSIPeripheral ssidev;
uint32_t bl_intensity;
uint32_t bl_power;
};
@ -612,7 +612,7 @@ static inline void spitz_bl_power(void *opaque, int line, int level)
spitz_bl_update(s);
}
static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
static uint32_t spitz_lcdtg_transfer(SSIPeripheral *dev, uint32_t value)
{
SpitzLCDTG *s = SPITZ_LCDTG(dev);
int addr;
@ -641,7 +641,7 @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
return 0;
}
static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
static void spitz_lcdtg_realize(SSIPeripheral *ssi, Error **errp)
{
SpitzLCDTG *s = SPITZ_LCDTG(ssi);
DeviceState *dev = DEVICE(s);
@ -667,12 +667,12 @@ OBJECT_DECLARE_SIMPLE_TYPE(CorgiSSPState, CORGI_SSP)
/* "Demux" the signal based on current chipselect */
struct CorgiSSPState {
SSISlave ssidev;
SSIPeripheral ssidev;
SSIBus *bus[3];
uint32_t enable[3];
};
static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
static uint32_t corgi_ssp_transfer(SSIPeripheral *dev, uint32_t value)
{
CorgiSSPState *s = CORGI_SSP(dev);
int i;
@ -700,7 +700,7 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
static void corgi_ssp_realize(SSISlave *d, Error **errp)
static void corgi_ssp_realize(SSIPeripheral *d, Error **errp)
{
DeviceState *dev = DEVICE(d);
CorgiSSPState *s = CORGI_SSP(d);
@ -715,14 +715,14 @@ static void spitz_ssp_attach(SpitzMachineState *sms)
{
void *bus;
sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
TYPE_CORGI_SSP);
sms->mux = ssi_create_peripheral(sms->mpu->ssp[CORGI_SSP_PORT - 1],
TYPE_CORGI_SSP);
bus = qdev_get_child_bus(sms->mux, "ssi0");
sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
sms->lcdtg = ssi_create_peripheral(bus, TYPE_SPITZ_LCDTG);
bus = qdev_get_child_bus(sms->mux, "ssi1");
sms->ads7846 = ssi_create_slave(bus, "ads7846");
sms->ads7846 = ssi_create_peripheral(bus, "ads7846");
qdev_connect_gpio_out(sms->ads7846, 0,
qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
@ -1204,7 +1204,7 @@ static const VMStateDescription vmstate_corgi_ssp_regs = {
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
VMSTATE_SSI_PERIPHERAL(ssidev, CorgiSSPState),
VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
VMSTATE_END_OF_LIST(),
}
@ -1213,7 +1213,7 @@ static const VMStateDescription vmstate_corgi_ssp_regs = {
static void corgi_ssp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = corgi_ssp_realize;
k->transfer = corgi_ssp_transfer;
@ -1222,7 +1222,7 @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
static const TypeInfo corgi_ssp_info = {
.name = TYPE_CORGI_SSP,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(CorgiSSPState),
.class_init = corgi_ssp_class_init,
};
@ -1232,7 +1232,7 @@ static const VMStateDescription vmstate_spitz_lcdtg_regs = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
VMSTATE_SSI_PERIPHERAL(ssidev, SpitzLCDTG),
VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
VMSTATE_UINT32(bl_power, SpitzLCDTG),
VMSTATE_END_OF_LIST(),
@ -1242,7 +1242,7 @@ static const VMStateDescription vmstate_spitz_lcdtg_regs = {
static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = spitz_lcdtg_realize;
k->transfer = spitz_lcdtg_transfer;
@ -1251,7 +1251,7 @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
static const TypeInfo spitz_lcdtg_info = {
.name = TYPE_SPITZ_LCDTG,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(SpitzLCDTG),
.class_init = spitz_lcdtg_class_init,
};

4
hw/arm/stellaris.c
View File

@ -1397,8 +1397,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
*/
bus = qdev_get_child_bus(dev, "ssi");
sddev = ssi_create_slave(bus, "ssi-sd");
ssddev = ssi_create_slave(bus, "ssd0323");
sddev = ssi_create_peripheral(bus, "ssi-sd");
ssddev = ssi_create_peripheral(bus, "ssd0323");
gpio_out[GPIO_D][0] = qemu_irq_split(
qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));

12
hw/arm/tosa.c
View File

@ -148,13 +148,13 @@ static void tosa_gpio_setup(PXA2xxState *cpu,
qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_USB_IN));
}
static uint32_t tosa_ssp_tansfer(SSISlave *dev, uint32_t value)
static uint32_t tosa_ssp_tansfer(SSIPeripheral *dev, uint32_t value)
{
fprintf(stderr, "TG: %u %02x\n", value >> 5, value & 0x1f);
return 0;
}
static void tosa_ssp_realize(SSISlave *dev, Error **errp)
static void tosa_ssp_realize(SSIPeripheral *dev, Error **errp)
{
/* Nothing to do. */
}
@ -225,7 +225,7 @@ static void tosa_tg_init(PXA2xxState *cpu)
{
I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
i2c_slave_create_simple(bus, TYPE_TOSA_DAC, DAC_BASE);
ssi_create_slave(cpu->ssp[1], "tosa-ssp");
ssi_create_peripheral(cpu->ssp[1], "tosa-ssp");
}
@ -292,7 +292,7 @@ static const TypeInfo tosa_dac_info = {
static void tosa_ssp_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = tosa_ssp_realize;
k->transfer = tosa_ssp_tansfer;
@ -300,8 +300,8 @@ static void tosa_ssp_class_init(ObjectClass *klass, void *data)
static const TypeInfo tosa_ssp_info = {
.name = "tosa-ssp",
.parent = TYPE_SSI_SLAVE,
.instance_size = sizeof(SSISlave),
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(SSIPeripheral),
.class_init = tosa_ssp_class_init,
};

9
hw/arm/vexpress.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
@ -560,7 +561,7 @@ static void vexpress_common_init(MachineState *machine)
/*
* If a bios file was provided, attempt to map it into memory
*/
if (bios_name) {
if (machine->firmware) {
char *fn;
int image_size;
@ -570,16 +571,16 @@ static void vexpress_common_init(MachineState *machine)
"but you cannot use both options at once");
exit(1);
}
fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (!fn) {
error_report("Could not find ROM image '%s'", bios_name);
error_report("Could not find ROM image '%s'", machine->firmware);
exit(1);
}
image_size = load_image_targphys(fn, map[VE_NORFLASH0],
VEXPRESS_FLASH_SIZE);
g_free(fn);
if (image_size < 0) {
error_report("Could not load ROM image '%s'", bios_name);
error_report("Could not load ROM image '%s'", machine->firmware);
exit(1);
}
}

3
hw/arm/virt.c
View File

@ -30,6 +30,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/option.h"
#include "monitor/qdev.h"
@ -1047,6 +1048,7 @@ static bool virt_firmware_init(VirtMachineState *vms,
MemoryRegion *secure_sysmem)
{
int i;
const char *bios_name;
BlockBackend *pflash_blk0;
/* Map legacy -drive if=pflash to machine properties */
@ -1059,6 +1061,7 @@ static bool virt_firmware_init(VirtMachineState *vms,
pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
bios_name = MACHINE(vms)->firmware;
if (bios_name) {
char *fname;
MemoryRegion *mr;

14
hw/arm/z2.c
View File

@ -104,7 +104,7 @@ static struct arm_boot_info z2_binfo = {
#define Z2_GPIO_LCD_CS 88
struct ZipitLCD {
SSISlave ssidev;
SSIPeripheral ssidev;
int32_t selected;
int32_t enabled;
uint8_t buf[3];
@ -115,7 +115,7 @@ struct ZipitLCD {
#define TYPE_ZIPIT_LCD "zipit-lcd"
OBJECT_DECLARE_SIMPLE_TYPE(ZipitLCD, ZIPIT_LCD)
static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
static uint32_t zipit_lcd_transfer(SSIPeripheral *dev, uint32_t value)
{
ZipitLCD *z = ZIPIT_LCD(dev);
uint16_t val;
@ -155,7 +155,7 @@ static void z2_lcd_cs(void *opaque, int line, int level)
z2_lcd->selected = !level;
}
static void zipit_lcd_realize(SSISlave *dev, Error **errp)
static void zipit_lcd_realize(SSIPeripheral *dev, Error **errp)
{
ZipitLCD *z = ZIPIT_LCD(dev);
z->selected = 0;
@ -168,7 +168,7 @@ static VMStateDescription vmstate_zipit_lcd_state = {
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_SSI_SLAVE(ssidev, ZipitLCD),
VMSTATE_SSI_PERIPHERAL(ssidev, ZipitLCD),
VMSTATE_INT32(selected, ZipitLCD),
VMSTATE_INT32(enabled, ZipitLCD),
VMSTATE_BUFFER(buf, ZipitLCD),
@ -181,7 +181,7 @@ static VMStateDescription vmstate_zipit_lcd_state = {
static void zipit_lcd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = zipit_lcd_realize;
k->transfer = zipit_lcd_transfer;
@ -190,7 +190,7 @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
static const TypeInfo zipit_lcd_info = {
.name = TYPE_ZIPIT_LCD,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(ZipitLCD),
.class_init = zipit_lcd_class_init,
};
@ -329,7 +329,7 @@ static void z2_init(MachineState *machine)
type_register_static(&zipit_lcd_info);
type_register_static(&aer915_info);
z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
z2_lcd = ssi_create_peripheral(mpu->ssp[1], TYPE_ZIPIT_LCD);
bus = pxa2xx_i2c_bus(mpu->i2c[0]);
i2c_slave_create_simple(bus, TYPE_AER915, 0x55);
wm = DEVICE(i2c_slave_create_simple(bus, TYPE_WM8750, 0x1b));

1
hw/avr/boot.c
View File

@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"

14
hw/block/m25p80.c
View File

@ -416,7 +416,7 @@ typedef enum {
#define M25P80_INTERNAL_DATA_BUFFER_SZ 16
struct Flash {
SSISlave parent_obj;
SSIPeripheral parent_obj;
BlockBackend *blk;
@ -458,7 +458,7 @@ struct Flash {
};
struct M25P80Class {
SSISlaveClass parent_class;
SSIPeripheralClass parent_class;
FlashPartInfo *pi;
};
@ -1170,7 +1170,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
}
}
static int m25p80_cs(SSISlave *ss, bool select)
static int m25p80_cs(SSIPeripheral *ss, bool select)
{
Flash *s = M25P80(ss);
@ -1190,7 +1190,7 @@ static int m25p80_cs(SSISlave *ss, bool select)
return 0;
}
static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
{
Flash *s = M25P80(ss);
uint32_t r = 0;
@ -1265,7 +1265,7 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
return r;
}
static void m25p80_realize(SSISlave *ss, Error **errp)
static void m25p80_realize(SSIPeripheral *ss, Error **errp)
{
Flash *s = M25P80(ss);
M25P80Class *mc = M25P80_GET_CLASS(s);
@ -1386,7 +1386,7 @@ static const VMStateDescription vmstate_m25p80 = {
static void m25p80_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
M25P80Class *mc = M25P80_CLASS(klass);
k->realize = m25p80_realize;
@ -1401,7 +1401,7 @@ static void m25p80_class_init(ObjectClass *klass, void *data)
static const TypeInfo m25p80_info = {
.name = TYPE_M25P80,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(Flash),
.class_size = sizeof(M25P80Class),
.abstract = true,

13
hw/char/serial.c
View File

@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "hw/char/serial.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
@ -338,11 +339,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
default:
case 0:
if (s->lcr & UART_LCR_DLAB) {
if (size == 1) {
s->divider = (s->divider & 0xff00) | val;
} else {
s->divider = val;
}
s->divider = deposit32(s->divider, 8 * addr, 8, val);
serial_update_parameters(s);
} else {
s->thr = (uint8_t) val;
@ -364,7 +361,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
break;
case 1:
if (s->lcr & UART_LCR_DLAB) {
s->divider = (s->divider & 0x00ff) | (val << 8);
s->divider = deposit32(s->divider, 8 * addr, 8, val);
serial_update_parameters(s);
} else {
uint8_t changed = (s->ier ^ val) & 0x0f;
@ -478,7 +475,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
default:
case 0:
if (s->lcr & UART_LCR_DLAB) {
ret = s->divider & 0xff;
ret = extract16(s->divider, 8 * addr, 8);
} else {
if(s->fcr & UART_FCR_FE) {
ret = fifo8_is_empty(&s->recv_fifo) ?
@ -502,7 +499,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
break;
case 1:
if (s->lcr & UART_LCR_DLAB) {
ret = (s->divider >> 8) & 0xff;
ret = extract16(s->divider, 8 * addr, 8);
} else {
ret = s->ier;
}

3
hw/core/generic-loader.c
View File

@ -35,6 +35,7 @@
#include "hw/sysbus.h"
#include "sysemu/dma.h"
#include "sysemu/reset.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
@ -154,7 +155,7 @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
if (size < 0 || s->force_raw) {
/* Default to the maximum size being the machine's ram size */
size = load_image_targphys_as(s->file, s->addr, ram_size, as);
size = load_image_targphys_as(s->file, s->addr, current_machine->ram_size, as);
} else {
s->addr = entry;
}

1
hw/core/loader.c
View File

@ -44,6 +44,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "trace.h"
#include "hw/hw.h"

56
hw/core/machine.c
View File

@ -877,9 +877,13 @@ static void machine_initfn(Object *obj)
MachineState *ms = MACHINE(obj);
MachineClass *mc = MACHINE_GET_CLASS(obj);
container_get(obj, "/peripheral");
container_get(obj, "/peripheral-anon");
ms->dump_guest_core = true;
ms->mem_merge = true;
ms->enable_graphics = true;
ms->kernel_cmdline = g_strdup("");
if (mc->nvdimm_supported) {
Object *obj = OBJECT(ms);
@ -1077,12 +1081,40 @@ MemoryRegion *machine_consume_memdev(MachineState *machine,
return ret;
}
bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp)
{
MachineClass *mc = MACHINE_GET_CLASS(ms);
mc->smp_parse(ms, opts);
/* sanity-check smp_cpus and max_cpus against mc */
if (ms->smp.cpus < mc->min_cpus) {
error_setg(errp, "Invalid SMP CPUs %d. The min CPUs "
"supported by machine '%s' is %d",
ms->smp.cpus,
mc->name, mc->min_cpus);
return false;
} else if (ms->smp.max_cpus > mc->max_cpus) {
error_setg(errp, "Invalid SMP CPUs %d. The max CPUs "
"supported by machine '%s' is %d",
current_machine->smp.max_cpus,
mc->name, mc->max_cpus);
return false;
}
return true;
}
void machine_run_board_init(MachineState *machine)
{
MachineClass *machine_class = MACHINE_GET_CLASS(machine);
ObjectClass *oc = object_class_by_name(machine->cpu_type);
CPUClass *cc;
/* This checkpoint is required by replay to separate prior clock
reading from the other reads, because timer polling functions query
clock values from the log. */
replay_checkpoint(CHECKPOINT_INIT);
if (machine->ram_memdev_id) {
Object *o;
o = object_resolve_path_type(machine->ram_memdev_id,
@ -1137,6 +1169,30 @@ void machine_run_board_init(MachineState *machine)
machine_class->init(machine);
}
static NotifierList machine_init_done_notifiers =
NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
bool machine_init_done;
void qemu_add_machine_init_done_notifier(Notifier *notify)
{
notifier_list_add(&machine_init_done_notifiers, notify);
if (machine_init_done) {
notify->notify(notify, NULL);
}
}
void qemu_remove_machine_init_done_notifier(Notifier *notify)
{
notifier_remove(notify);
}
void qemu_run_machine_init_done_notifiers(void)
{
machine_init_done = true;
notifier_list_notify(&machine_init_done_notifiers, NULL);
}
static const TypeInfo machine_info = {
.name = TYPE_MACHINE,
.parent = TYPE_OBJECT,

10
hw/core/numa.c
View File

@ -642,7 +642,7 @@ void numa_complete_configuration(MachineState *ms)
/*
* If memory hotplug is enabled (slot > 0) or memory devices are enabled
* (ms->maxram_size > ram_size) but without '-numa' options explicitly on
* (ms->maxram_size > ms->ram_size) but without '-numa' options explicitly on
* CLI, guests will break.
*
* Windows: won't enable memory hotplug without SRAT table at all
@ -663,7 +663,7 @@ void numa_complete_configuration(MachineState *ms)
mc->auto_enable_numa)) {
NumaNodeOptions node = { };
parse_numa_node(ms, &node, &error_abort);
numa_info[0].node_mem = ram_size;
numa_info[0].node_mem = ms->ram_size;
}
assert(max_numa_nodeid <= MAX_NODES);
@ -687,10 +687,10 @@ void numa_complete_configuration(MachineState *ms)
for (i = 0; i < ms->numa_state->num_nodes; i++) {
numa_total += numa_info[i].node_mem;
}
if (numa_total != ram_size) {
if (numa_total != ms->ram_size) {
error_report("total memory for NUMA nodes (0x%" PRIx64 ")"
" should equal RAM size (0x" RAM_ADDR_FMT ")",
numa_total, ram_size);
numa_total, ms->ram_size);
exit(1);
}
@ -702,7 +702,7 @@ void numa_complete_configuration(MachineState *ms)
}
ms->ram = g_new(MemoryRegion, 1);
memory_region_init(ms->ram, OBJECT(ms), mc->default_ram_id,
ram_size);
ms->ram_size);
numa_init_memdev_container(ms, ms->ram);
}
/* QEMU needs at least all unique node pair distances to build

20
hw/core/stream.c
View File

@ -3,32 +3,32 @@
#include "qemu/module.h"
size_t
stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop)
stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop)
{
StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
return k->push(sink, buf, len, eop);
}
bool
stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
void *notify_opaque)
{
StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
return k->can_push ? k->can_push(sink, notify, notify_opaque) : true;
}
static const TypeInfo stream_slave_info = {
.name = TYPE_STREAM_SLAVE,
static const TypeInfo stream_sink_info = {
.name = TYPE_STREAM_SINK,
.parent = TYPE_INTERFACE,
.class_size = sizeof(StreamSlaveClass),
.class_size = sizeof(StreamSinkClass),
};
static void stream_slave_register_types(void)
static void stream_sink_register_types(void)
{
type_register_static(&stream_slave_info);
type_register_static(&stream_sink_info);
}
type_init(stream_slave_register_types)
type_init(stream_sink_register_types)

1
hw/cris/axis_dev88.c
View File

@ -333,6 +333,7 @@ void axisdev88_init(MachineState *machine)
if (kernel_filename) {
li.image_filename = kernel_filename;
li.cmdline = kernel_cmdline;
li.ram_size = machine->ram_size;
cris_load_image(cpu, &li);
} else if (!qtest_enabled()) {
fprintf(stderr, "Kernel image must be specified\n");

2
hw/cris/boot.c
View File

@ -81,7 +81,7 @@ void cris_load_image(CRISCPU *cpu, struct cris_load_info *li)
if (image_size < 0) {
/* Takes a kimage from the axis devboard SDK. */
image_size = load_image_targphys(li->image_filename, 0x40004000,
ram_size);
li->ram_size);
li->entry = 0x40004000;
}

1
hw/cris/boot.h
View File

@ -6,6 +6,7 @@ struct cris_load_info
const char *image_filename;
const char *cmdline;
int image_size;
ram_addr_t ram_size;
hwaddr entry;
};

12
hw/display/ads7846.c
View File

@ -19,7 +19,7 @@
#include "qom/object.h"
struct ADS7846State {
SSISlave ssidev;
SSIPeripheral ssidev;
qemu_irq interrupt;
int input[8];
@ -63,7 +63,7 @@ static void ads7846_int_update(ADS7846State *s)
qemu_set_irq(s->interrupt, s->pressure == 0);
}
static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
static uint32_t ads7846_transfer(SSIPeripheral *dev, uint32_t value)
{
ADS7846State *s = ADS7846(dev);
@ -131,7 +131,7 @@ static const VMStateDescription vmstate_ads7846 = {
.minimum_version_id = 1,
.post_load = ads7856_post_load,
.fields = (VMStateField[]) {
VMSTATE_SSI_SLAVE(ssidev, ADS7846State),
VMSTATE_SSI_PERIPHERAL(ssidev, ADS7846State),
VMSTATE_INT32_ARRAY(input, ADS7846State, 8),
VMSTATE_INT32(noise, ADS7846State),
VMSTATE_INT32(cycle, ADS7846State),
@ -140,7 +140,7 @@ static const VMStateDescription vmstate_ads7846 = {
}
};
static void ads7846_realize(SSISlave *d, Error **errp)
static void ads7846_realize(SSIPeripheral *d, Error **errp)
{
DeviceState *dev = DEVICE(d);
ADS7846State *s = ADS7846(d);
@ -164,7 +164,7 @@ static void ads7846_realize(SSISlave *d, Error **errp)
static void ads7846_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = ads7846_realize;
k->transfer = ads7846_transfer;
@ -173,7 +173,7 @@ static void ads7846_class_init(ObjectClass *klass, void *data)
static const TypeInfo ads7846_info = {
.name = TYPE_ADS7846,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(ADS7846State),
.class_init = ads7846_class_init,
};

1
hw/display/cg3.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "ui/console.h"

5
hw/display/pxa2xx_lcd.c
View File

@ -17,6 +17,7 @@
#include "ui/console.h"
#include "hw/arm/pxa.h"
#include "ui/pixel_ops.h"
#include "hw/boards.h"
/* FIXME: For graphic_rotate. Should probably be done in common code. */
#include "sysemu/sysemu.h"
#include "framebuffer.h"
@ -305,7 +306,7 @@ static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
descptr = s->dma_ch[i].descriptor;
if (!((descptr >= PXA2XX_SDRAM_BASE && descptr +
sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size) ||
sizeof(desc) <= PXA2XX_SDRAM_BASE + current_machine->ram_size) ||
(descptr >= PXA2XX_INTERNAL_BASE && descptr + sizeof(desc) <=
PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
continue;
@ -850,7 +851,7 @@ static void pxa2xx_update_display(void *opaque)
}
fbptr = s->dma_ch[ch].source;
if (!((fbptr >= PXA2XX_SDRAM_BASE &&
fbptr <= PXA2XX_SDRAM_BASE + ram_size) ||
fbptr <= PXA2XX_SDRAM_BASE + current_machine->ram_size) ||
(fbptr >= PXA2XX_INTERNAL_BASE &&
fbptr <= PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
pxa2xx_dma_ber_set(s, ch);

12
hw/display/ssd0323.c
View File

@ -49,7 +49,7 @@ enum ssd0323_mode
};
struct ssd0323_state {
SSISlave ssidev;
SSIPeripheral ssidev;
QemuConsole *con;
uint32_t cmd_len;
@ -71,7 +71,7 @@ struct ssd0323_state {
OBJECT_DECLARE_SIMPLE_TYPE(ssd0323_state, SSD0323)
static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
static uint32_t ssd0323_transfer(SSIPeripheral *dev, uint32_t data)
{
ssd0323_state *s = SSD0323(dev);
@ -338,7 +338,7 @@ static const VMStateDescription vmstate_ssd0323 = {
VMSTATE_INT32(remap, ssd0323_state),
VMSTATE_UINT32(mode, ssd0323_state),
VMSTATE_BUFFER(framebuffer, ssd0323_state),
VMSTATE_SSI_SLAVE(ssidev, ssd0323_state),
VMSTATE_SSI_PERIPHERAL(ssidev, ssd0323_state),
VMSTATE_END_OF_LIST()
}
};
@ -348,7 +348,7 @@ static const GraphicHwOps ssd0323_ops = {
.gfx_update = ssd0323_update_display,
};
static void ssd0323_realize(SSISlave *d, Error **errp)
static void ssd0323_realize(SSIPeripheral *d, Error **errp)
{
DeviceState *dev = DEVICE(d);
ssd0323_state *s = SSD0323(d);
@ -364,7 +364,7 @@ static void ssd0323_realize(SSISlave *d, Error **errp)
static void ssd0323_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = ssd0323_realize;
k->transfer = ssd0323_transfer;
@ -375,7 +375,7 @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
static const TypeInfo ssd0323_info = {
.name = TYPE_SSD0323,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(ssd0323_state),
.class_init = ssd0323_class_init,
};

1
hw/display/tcx.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"

58
hw/dma/xilinx_axidma.c
View File

@ -45,11 +45,11 @@
OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIDMA, XILINX_AXI_DMA)
typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_DATA_STREAM,
typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_DATA_STREAM,
TYPE_XILINX_AXI_DMA_DATA_STREAM)
DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSlave, XILINX_AXI_DMA_CONTROL_STREAM,
DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_CONTROL_STREAM,
TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
#define R_DMACR (0x00 / 4)
@ -115,7 +115,7 @@ struct Stream {
unsigned char txbuf[16 * 1024];
};
struct XilinxAXIDMAStreamSlave {
struct XilinxAXIDMAStreamSink {
Object parent;
struct XilinxAXIDMA *dma;
@ -128,10 +128,10 @@ struct XilinxAXIDMA {
AddressSpace as;
uint32_t freqhz;
StreamSlave *tx_data_dev;
StreamSlave *tx_control_dev;
XilinxAXIDMAStreamSlave rx_data_dev;
XilinxAXIDMAStreamSlave rx_control_dev;
StreamSink *tx_data_dev;
StreamSink *tx_control_dev;
XilinxAXIDMAStreamSink rx_data_dev;
XilinxAXIDMAStreamSink rx_control_dev;
struct Stream streams[2];
@ -261,8 +261,8 @@ static void stream_complete(struct Stream *s)
ptimer_transaction_commit(s->ptimer);
}
static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
StreamSlave *tx_control_dev)
static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
StreamSink *tx_control_dev)
{
uint32_t prev_d;
uint32_t txlen;
@ -384,10 +384,10 @@ static void xilinx_axidma_reset(DeviceState *dev)
}
static size_t
xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
size_t len, bool eop)
{
XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
struct Stream *s = &cs->dma->streams[1];
if (len != CONTROL_PAYLOAD_SIZE) {
@ -400,11 +400,11 @@ xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
}
static bool
xilinx_axidma_data_stream_can_push(StreamSlave *obj,
xilinx_axidma_data_stream_can_push(StreamSink *obj,
StreamCanPushNotifyFn notify,
void *notify_opaque)
{
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
struct Stream *s = &ds->dma->streams[1];
if (!stream_running(s) || stream_idle(s)) {
@ -417,10 +417,10 @@ xilinx_axidma_data_stream_can_push(StreamSlave *obj,
}
static size_t
xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
bool eop)
{
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
struct Stream *s = &ds->dma->streams[1];
size_t ret;
@ -531,8 +531,8 @@ static const MemoryRegionOps axidma_ops = {
static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
{
XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
&s->rx_control_dev);
int i;
@ -588,9 +588,9 @@ static void xilinx_axidma_init(Object *obj)
static Property axidma_properties[] = {
DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_END_OF_LIST(),
};
@ -603,21 +603,21 @@ static void axidma_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, axidma_properties);
}
static StreamSlaveClass xilinx_axidma_data_stream_class = {
static StreamSinkClass xilinx_axidma_data_stream_class = {
.push = xilinx_axidma_data_stream_push,
.can_push = xilinx_axidma_data_stream_can_push,
};
static StreamSlaveClass xilinx_axidma_control_stream_class = {
static StreamSinkClass xilinx_axidma_control_stream_class = {
.push = xilinx_axidma_control_stream_push,
};
static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
{
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
ssc->push = ((StreamSlaveClass *)data)->push;
ssc->can_push = ((StreamSlaveClass *)data)->can_push;
ssc->push = ((StreamSinkClass *)data)->push;
ssc->can_push = ((StreamSinkClass *)data)->can_push;
}
static const TypeInfo axidma_info = {
@ -631,11 +631,11 @@ static const TypeInfo axidma_info = {
static const TypeInfo xilinx_axidma_data_stream_info = {
.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
.parent = TYPE_OBJECT,
.instance_size = sizeof(XilinxAXIDMAStreamSlave),
.instance_size = sizeof(XilinxAXIDMAStreamSink),
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_data_stream_class,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SLAVE },
{ TYPE_STREAM_SINK },
{ }
}
};
@ -643,11 +643,11 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
static const TypeInfo xilinx_axidma_control_stream_info = {
.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
.parent = TYPE_OBJECT,
.instance_size = sizeof(XilinxAXIDMAStreamSlave),
.instance_size = sizeof(XilinxAXIDMAStreamSink),
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_control_stream_class,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SLAVE },
{ TYPE_STREAM_SINK },
{ }
}
};

14
hw/hppa/machine.c
View File

@ -5,6 +5,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "elf.h"
#include "hw/loader.h"
@ -97,7 +98,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
fw_cfg = fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ram_size);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
val = cpu_to_le64(MIN_SEABIOS_HPPA_VERSION);
fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
@ -213,8 +214,7 @@ static void machine_hppa_init(MachineState *machine)
but one explicitly written for the emulation, we might as
well load it directly from an ELF image. */
firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
bios_name ? bios_name :
"hppa-firmware.img");
machine->firmware ?: "hppa-firmware.img");
if (firmware_filename == NULL) {
error_report("no firmware provided");
exit(1);
@ -289,7 +289,7 @@ static void machine_hppa_init(MachineState *machine)
(1) Due to sign-extension problems and PDC,
put the initrd no higher than 1G.
(2) Reserve 64k for stack. */
initrd_base = MIN(ram_size, 1 * GiB);
initrd_base = MIN(machine->ram_size, 1 * GiB);
initrd_base = initrd_base - 64 * KiB;
initrd_base = (initrd_base - initrd_size) & TARGET_PAGE_MASK;
@ -317,7 +317,7 @@ static void machine_hppa_init(MachineState *machine)
* various parameters in registers. After firmware initialization,
* firmware will start the Linux kernel with ramdisk and cmdline.
*/
cpu[0]->env.gr[26] = ram_size;
cpu[0]->env.gr[26] = machine->ram_size;
cpu[0]->env.gr[25] = kernel_entry;
/* tell firmware how many SMP CPUs to present in inventory table */
@ -343,11 +343,11 @@ static void hppa_machine_reset(MachineState *ms)
}
/* already initialized by machine_hppa_init()? */
if (cpu[0]->env.gr[26] == ram_size) {
if (cpu[0]->env.gr[26] == ms->ram_size) {
return;
}
cpu[0]->env.gr[26] = ram_size;
cpu[0]->env.gr[26] = ms->ram_size;
cpu[0]->env.gr[25] = 0; /* no firmware boot menu */
cpu[0]->env.gr[24] = 'c';
/* gr22/gr23 unused, no initrd while reboot. */

2
hw/i386/fw_cfg.c
View File

@ -118,7 +118,7 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms,
* "etc/max-cpus" actually being apic_id_limit
*/
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
#ifdef CONFIG_ACPI
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
acpi_tables, acpi_tables_len);

7
hw/i386/kvm/apic.c
View File

@ -183,6 +183,13 @@ static void kvm_send_msi(MSIMessage *msg)
{
int ret;
/*
* The message has already passed through interrupt remapping if enabled,
* but the legacy extended destination ID in low bits still needs to be
* handled.
*/
msg->address = kvm_swizzle_msi_ext_dest_id(msg->address);
ret = kvm_irqchip_send_msi(kvm_state, *msg);
if (ret < 0) {
fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n",

7
hw/i386/microvm.c
View File

@ -158,6 +158,7 @@ static int microvm_ioapics(MicrovmMachineState *mms)
static void microvm_devices_init(MicrovmMachineState *mms)
{
const char *default_firmware;
X86MachineState *x86ms = X86_MACHINE(mms);
ISABus *isa_bus;
ISADevice *rtc_state;
@ -274,12 +275,10 @@ static void microvm_devices_init(MicrovmMachineState *mms)
serial_hds_isa_init(isa_bus, 0, 1);
}
if (bios_name == NULL) {
bios_name = x86_machine_is_acpi_enabled(x86ms)
default_firmware = x86_machine_is_acpi_enabled(x86ms)
? MICROVM_BIOS_FILENAME
: MICROVM_QBOOT_FILENAME;
}
x86_bios_rom_init(get_system_memory(), true);
x86_bios_rom_init(MACHINE(mms), default_firmware, get_system_memory(), true);
}
static void microvm_memory_init(MicrovmMachineState *mms)

16
hw/i386/pc.c
View File

@ -104,6 +104,7 @@ const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
GlobalProperty pc_compat_5_1[] = {
{ "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
{ TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
};
const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
@ -796,17 +797,12 @@ void pc_machine_done(Notifier *notifier, void *data)
fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
}
if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
iommu->intr_eim != ON_OFF_AUTO_ON) {
error_report("current -smp configuration requires "
"Extended Interrupt Mode enabled. "
"You can add an IOMMU using: "
"-device intel-iommu,intremap=on,eim=on");
exit(EXIT_FAILURE);
}
if (x86ms->apic_id_limit > 255 && !xen_enabled() &&
!kvm_irqchip_in_kernel()) {
error_report("current -smp configuration requires kernel "
"irqchip support.");
exit(EXIT_FAILURE);
}
}

4
hw/i386/pc_sysfw.c
View File

@ -213,7 +213,7 @@ void pc_system_firmware_init(PCMachineState *pcms,
BlockBackend *pflash_blk[ARRAY_SIZE(pcms->flash)];
if (!pcmc->pci_enabled) {
x86_bios_rom_init(rom_memory, true);
x86_bios_rom_init(MACHINE(pcms), "bios.bin", rom_memory, true);
return;
}
@ -234,7 +234,7 @@ void pc_system_firmware_init(PCMachineState *pcms,
if (!pflash_blk[0]) {
/* Machine property pflash0 not set, use ROM mode */
x86_bios_rom_init(rom_memory, false);
x86_bios_rom_init(MACHINE(pcms), "bios.bin", rom_memory, false);
} else {
if (kvm_enabled() && !kvm_readonly_mem_enabled()) {
/*

3
hw/i386/vmport.c
View File

@ -32,6 +32,7 @@
#include "hw/isa/isa.h"
#include "hw/i386/vmport.h"
#include "hw/qdev-properties.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "sysemu/hw_accel.h"
#include "sysemu/qtest.h"
@ -188,7 +189,7 @@ static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr)
return -1;
}
cpu->env.regs[R_EBX] = 0x1177;
return ram_size;
return current_machine->ram_size;
}
static uint32_t vmport_cmd_get_hz(void *opaque, uint32_t addr)

17
hw/i386/x86.c
View File

@ -26,11 +26,13 @@
#include "qemu/cutils.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "qapi/qapi-visit-common.h"
#include "qapi/visitor.h"
#include "sysemu/qtest.h"
#include "sysemu/whpx.h"
#include "sysemu/numa.h"
#include "sysemu/replay.h"
#include "sysemu/sysemu.h"
@ -54,8 +56,6 @@
#include CONFIG_DEVICES
#include "kvm_i386.h"
#define BIOS_FILENAME "bios.bin"
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
@ -532,7 +532,8 @@ static void pic_irq_request(void *opaque, int irq, int level)
X86CPU *cpu = X86_CPU(cs);
trace_x86_pic_interrupt(irq, level);
if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
if (cpu->apic_state && !kvm_irqchip_in_kernel() &&
!whpx_apic_in_platform()) {
CPU_FOREACH(cs) {
cpu = X86_CPU(cs);
if (apic_accept_pic_intr(cpu->apic_state)) {
@ -558,7 +559,7 @@ int cpu_get_pic_interrupt(CPUX86State *env)
X86CPU *cpu = env_archcpu(env);
int intno;
if (!kvm_irqchip_in_kernel()) {
if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) {
intno = apic_get_interrupt(cpu->apic_state);
if (intno >= 0) {
return intno;
@ -1078,17 +1079,17 @@ void x86_load_linux(X86MachineState *x86ms,
nb_option_roms++;
}
void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
MemoryRegion *rom_memory, bool isapc_ram_fw)
{
const char *bios_name;
char *filename;
MemoryRegion *bios, *isa_bios;
int bios_size, isa_bios_size;
int ret;
/* BIOS load */
if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
}
bios_name = ms->firmware ?: default_firmware;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = get_image_size(filename);

2
hw/i386/xen/xen-hvm.c
View File

@ -1493,7 +1493,7 @@ void xen_hvm_init_pc(PCMachineState *pcms, MemoryRegion **ram_memory)
#else
xen_map_cache_init(NULL, state);
#endif
xen_ram_init(pcms, ram_size, ram_memory);
xen_ram_init(pcms, ms->ram_size, ram_memory);
qemu_add_vm_change_state_handler(xen_hvm_change_state_handler, state);

3
hw/intc/apic_common.c
View File

@ -27,6 +27,7 @@
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#include "trace.h"
#include "hw/boards.h"
#include "sysemu/hax.h"
#include "sysemu/kvm.h"
#include "hw/qdev-properties.h"
@ -297,7 +298,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
!hax_enabled() && ram_size >= 1024 * 1024) {
!hax_enabled() && current_machine->ram_size >= 1024 * 1024) {
vapic = sysbus_create_simple("kvmvapic", -1, NULL);
}
s->vapic = vapic;

5
hw/lm32/milkymist.c
View File

@ -21,6 +21,7 @@
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
@ -108,6 +109,7 @@ static void
milkymist_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *bios_name = machine->firmware ?: BIOS_FILENAME;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@ -162,9 +164,6 @@ milkymist_init(MachineState *machine)
}
/* load bios rom */
if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
}
bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (bios_filename) {

4
hw/m68k/mcf5206.c
View File

@ -10,6 +10,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/boards.h"
#include "hw/irq.h"
#include "hw/m68k/mcf.h"
#include "qemu/timer.h"
@ -312,8 +313,9 @@ static uint64_t m5206_mbar_read(m5206_mbar_state *s,
/* FIXME: currently hardcoded to 128Mb. */
{
uint32_t mask = ~0;
while (mask > ram_size)
while (mask > current_machine->ram_size) {
mask >>= 1;
}
return mask & 0x0ffe0000;
}
case 0x5c: return 1; /* DRAM bank 1 empty. */

14
hw/m68k/mcf5208.c
View File

@ -12,6 +12,7 @@
#include "qemu/log.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/irq.h"
#include "hw/m68k/mcf.h"
@ -157,8 +158,9 @@ static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
{
int n;
for (n = 0; n < 32; n++) {
if (ram_size < (2u << n))
if (current_machine->ram_size < (2u << n)) {
break;
}
}
return (n - 1) | 0x40000000;
}
@ -301,17 +303,17 @@ static void mcf5208evb_init(MachineState *machine)
/* 0xfc0a8000 SDRAM controller. */
/* Load firmware */
if (bios_name) {
if (machine->firmware) {
char *fn;
uint8_t *ptr;
fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
if (!fn) {
error_report("Could not find ROM image '%s'", bios_name);
error_report("Could not find ROM image '%s'", machine->firmware);
exit(1);
}
if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) {
error_report("Could not load ROM image '%s'", bios_name);
error_report("Could not load ROM image '%s'", machine->firmware);
exit(1);
}
g_free(fn);
@ -323,7 +325,7 @@ static void mcf5208evb_init(MachineState *machine)
/* Load kernel. */
if (!kernel_filename) {
if (qtest_enabled() || bios_name) {
if (qtest_enabled() || machine->firmware) {
return;
}
error_report("Kernel image must be specified");

4
hw/m68k/next-cube.c
View File

@ -868,6 +868,7 @@ static void next_cube_init(MachineState *machine)
MemoryRegion *bmapm1 = g_new(MemoryRegion, 1);
MemoryRegion *bmapm2 = g_new(MemoryRegion, 1);
MemoryRegion *sysmem = get_system_memory();
const char *bios_name = machine->firmware ?: ROM_FILE;
NeXTState *ns = NEXT_MACHINE(machine);
DeviceState *dev;
@ -924,9 +925,6 @@ static void next_cube_init(MachineState *machine)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000);
/* Load ROM here */
if (bios_name == NULL) {
bios_name = ROM_FILE;
}
/* still not sure if the rom should also be mapped at 0x0*/
memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal);
memory_region_add_subregion(sysmem, 0x01000000, rom);

5
hw/m68k/q800.c
View File

@ -23,6 +23,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "sysemu/sysemu.h"
#include "cpu.h"
#include "hw/hw.h"
@ -167,6 +168,7 @@ static void q800_init(MachineState *machine)
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *bios_name = machine->firmware ?: MACROM_FILENAME;
hwaddr parameters_base;
CPUState *cs;
DeviceState *dev;
@ -400,9 +402,6 @@ static void q800_init(MachineState *machine)
rom = g_malloc(sizeof(*rom));
memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
&error_abort);
if (bios_name == NULL) {
bios_name = MACROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);

9
hw/microblaze/boot.c
View File

@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "qemu/option.h"
#include "qemu/config-file.h"
@ -170,7 +171,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
/* Not an ELF image nor an u-boot image, try a RAW image. */
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename, ddr_base,
ram_size);
ramsize);
boot_info.bootstrap_pc = ddr_base;
high = (ddr_base + kernel_size + 3) & ~3;
}
@ -185,11 +186,11 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
initrd_size = load_ramdisk(initrd_filename,
boot_info.initrd_start,
ram_size - initrd_offset);
ramsize - initrd_offset);
if (initrd_size < 0) {
initrd_size = load_image_targphys(initrd_filename,
boot_info.initrd_start,
ram_size - initrd_offset);
ramsize - initrd_offset);
}
if (initrd_size < 0) {
error_report("could not load initrd '%s'",
@ -206,7 +207,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
}
/* Provide a device-tree. */
boot_info.fdt = boot_info.cmdline + 4096;
microblaze_load_dtb(boot_info.fdt, ram_size,
microblaze_load_dtb(boot_info.fdt, ramsize,
boot_info.initrd_start,
boot_info.initrd_end,
kernel_cmdline,

11
hw/mips/fuloong2e.c
View File

@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
@ -134,14 +135,14 @@ static int64_t load_kernel(CPUMIPSState *env)
initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
initrd_offset = ROUND_UP(kernel_high, INITRD_PAGE_SIZE);
if (initrd_offset + initrd_size > ram_size) {
if (initrd_offset + initrd_size > loaderparams.ram_size) {
error_report("memory too small for initial ram disk '%s'",
loaderparams.initrd_filename);
exit(1);
}
initrd_size = load_image_targphys(loaderparams.initrd_filename,
initrd_offset,
ram_size - initrd_offset);
loaderparams.ram_size - initrd_offset);
}
if (initrd_size == (target_ulong) -1) {
error_report("could not load initial ram disk '%s'",
@ -338,7 +339,7 @@ static void mips_fuloong2e_init(MachineState *machine)
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
bios_name ?: FULOONG_BIOSNAME);
machine->firmware ?: FULOONG_BIOSNAME);
if (filename) {
bios_size = load_image_targphys(filename, 0x1fc00000LL,
BIOS_SIZE);
@ -348,8 +349,8 @@ static void mips_fuloong2e_init(MachineState *machine)
}
if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
bios_name && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
machine->firmware && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", machine->firmware);
exit(1);
}
}

7
hw/mips/jazz.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "hw/clock.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
@ -218,7 +219,7 @@ static void mips_jazz_init(MachineState *machine,
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name ?: BIOS_FILENAME);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
@ -227,8 +228,8 @@ static void mips_jazz_init(MachineState *machine,
bios_size = -1;
}
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE)
&& bios_name && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
&& machine->firmware && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", machine->firmware);
exit(1);
}

9
hw/mips/malta.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/clock.h"
#include "hw/southbridge/piix.h"
@ -1087,7 +1088,7 @@ static int64_t load_kernel(void)
}
initrd_size = load_image_targphys(loaderparams.initrd_filename,
initrd_offset,
ram_size - initrd_offset);
loaderparams.ram_size - initrd_offset);
}
if (initrd_size == (target_ulong) -1) {
error_report("could not load initial ram disk '%s'",
@ -1333,7 +1334,7 @@ void mips_malta_init(MachineState *machine)
if (!dinfo) {
/* Load a BIOS image. */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
bios_name ?: BIOS_FILENAME);
machine->firmware ?: BIOS_FILENAME);
if (filename) {
bios_size = load_image_targphys(filename, FLASH_ADDRESS,
BIOS_SIZE);
@ -1342,8 +1343,8 @@ void mips_malta_init(MachineState *machine)
bios_size = -1;
}
if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
bios_name && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
machine->firmware && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", machine->firmware);
exit(1);
}
}

7
hw/mips/mipssim.c
View File

@ -28,6 +28,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/clock.h"
#include "hw/mips/mips.h"
@ -177,7 +178,7 @@ mips_mipssim_init(MachineState *machine)
/* Map the BIOS / boot exception handler. */
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* Load a BIOS / boot exception handler image. */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name ?: BIOS_FILENAME);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware ?: BIOS_FILENAME);
if (filename) {
bios_size = load_image_targphys(filename, 0x1fc00000LL, BIOS_SIZE);
g_free(filename);
@ -185,9 +186,9 @@ mips_mipssim_init(MachineState *machine)
bios_size = -1;
}
if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
bios_name && !qtest_enabled()) {
machine->firmware && !qtest_enabled()) {
/* Bail out if we have neither a kernel image nor boot vector code. */
error_report("Could not load MIPS bios '%s'", bios_name);
error_report("Could not load MIPS bios '%s'", machine->firmware);
exit(1);
} else {
/* We have a boot vector start address. */

18
hw/misc/max111x.c
View File

@ -85,7 +85,7 @@ static void max111x_write(MAX111xState *s, uint32_t value)
qemu_irq_raise(s->interrupt);
}
static uint32_t max111x_transfer(SSISlave *dev, uint32_t value)
static uint32_t max111x_transfer(SSIPeripheral *dev, uint32_t value)
{
MAX111xState *s = MAX_111X(dev);
max111x_write(s, value);
@ -97,7 +97,7 @@ static const VMStateDescription vmstate_max111x = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_SSI_SLAVE(parent_obj, MAX111xState),
VMSTATE_SSI_PERIPHERAL(parent_obj, MAX111xState),
VMSTATE_UINT8(tb1, MAX111xState),
VMSTATE_UINT8(rb2, MAX111xState),
VMSTATE_UINT8(rb3, MAX111xState),
@ -117,7 +117,7 @@ static void max111x_input_set(void *opaque, int line, int value)
s->input[line] = value;
}
static int max111x_init(SSISlave *d, int inputs)
static int max111x_init(SSIPeripheral *d, int inputs)
{
DeviceState *dev = DEVICE(d);
MAX111xState *s = MAX_111X(dev);
@ -130,12 +130,12 @@ static int max111x_init(SSISlave *d, int inputs)
return 0;
}
static void max1110_realize(SSISlave *dev, Error **errp)
static void max1110_realize(SSIPeripheral *dev, Error **errp)
{
max111x_init(dev, 8);
}
static void max1111_realize(SSISlave *dev, Error **errp)
static void max1111_realize(SSIPeripheral *dev, Error **errp)
{
max111x_init(dev, 4);
}
@ -179,7 +179,7 @@ static Property max1111_properties[] = {
static void max111x_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->transfer = max111x_transfer;
@ -190,7 +190,7 @@ static void max111x_class_init(ObjectClass *klass, void *data)
static const TypeInfo max111x_info = {
.name = TYPE_MAX_111X,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(MAX111xState),
.class_init = max111x_class_init,
.abstract = true,
@ -198,7 +198,7 @@ static const TypeInfo max111x_info = {
static void max1110_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->realize = max1110_realize;
@ -213,7 +213,7 @@ static const TypeInfo max1110_info = {
static void max1111_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->realize = max1111_realize;

8
hw/moxie/moxiesim.c
View File

@ -82,7 +82,7 @@ static void load_kernel(MoxieCPU *cpu, LoaderParams *loader_params)
}
initrd_size = load_image_targphys(loader_params->initrd_filename,
initrd_offset,
ram_size);
loader_params->ram_size);
}
if (initrd_size == (target_ulong)-1) {
error_report("could not load initial ram disk '%s'",
@ -133,9 +133,9 @@ static void moxiesim_init(MachineState *machine)
loader_params.initrd_filename = initrd_filename;
load_kernel(cpu, &loader_params);
}
if (bios_name) {
if (load_image_targphys(bios_name, FIRMWARE_BASE, FIRMWARE_SIZE) < 0) {
error_report("Failed to load firmware '%s'", bios_name);
if (machine->firmware) {
if (load_image_targphys(machine->firmware, FIRMWARE_BASE, FIRMWARE_SIZE) < 0) {
error_report("Failed to load firmware '%s'", machine->firmware);
}
}

44
hw/net/xilinx_axienet.c
View File

@ -45,11 +45,11 @@
OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET)
typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_DATA_STREAM,
typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_DATA_STREAM,
TYPE_XILINX_AXI_ENET_DATA_STREAM)
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_CONTROL_STREAM,
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_CONTROL_STREAM,
TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
/* Advertisement control register. */
@ -310,7 +310,7 @@ struct TEMAC {
};
struct XilinxAXIEnetStreamSlave {
struct XilinxAXIEnetStreamSink {
Object parent;
struct XilinxAXIEnet *enet;
@ -320,10 +320,10 @@ struct XilinxAXIEnet {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
StreamSlave *tx_data_dev;
StreamSlave *tx_control_dev;
XilinxAXIEnetStreamSlave rx_data_dev;
XilinxAXIEnetStreamSlave rx_control_dev;
StreamSink *tx_data_dev;
StreamSink *tx_control_dev;
XilinxAXIEnetStreamSink rx_data_dev;
XilinxAXIEnetStreamSink rx_control_dev;
NICState *nic;
NICConf conf;
@ -852,11 +852,11 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
}
static size_t
xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
bool eop)
{
int i;
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
XilinxAXIEnet *s = cs->enet;
assert(eop);
@ -874,10 +874,10 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
}
static size_t
xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
bool eop)
{
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
XilinxAXIEnet *s = ds->enet;
/* TX enable ? */
@ -951,8 +951,8 @@ static NetClientInfo net_xilinx_enet_info = {
static void xilinx_enet_realize(DeviceState *dev, Error **errp)
{
XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
&s->rx_control_dev);
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
@ -1002,9 +1002,9 @@ static Property xilinx_enet_properties[] = {
DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_END_OF_LIST(),
};
@ -1020,14 +1020,14 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data)
static void xilinx_enet_control_stream_class_init(ObjectClass *klass,
void *data)
{
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
ssc->push = xilinx_axienet_control_stream_push;
}
static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data)
{
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
ssc->push = xilinx_axienet_data_stream_push;
}
@ -1043,10 +1043,10 @@ static const TypeInfo xilinx_enet_info = {
static const TypeInfo xilinx_enet_data_stream_info = {
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
.parent = TYPE_OBJECT,
.instance_size = sizeof(XilinxAXIEnetStreamSlave),
.instance_size = sizeof(XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_data_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SLAVE },
{ TYPE_STREAM_SINK },
{ }
}
};
@ -1054,10 +1054,10 @@ static const TypeInfo xilinx_enet_data_stream_info = {
static const TypeInfo xilinx_enet_control_stream_info = {
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
.parent = TYPE_OBJECT,
.instance_size = sizeof(XilinxAXIEnetStreamSlave),
.instance_size = sizeof(XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_control_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SLAVE },
{ TYPE_STREAM_SINK },
{ }
}
};

9
hw/nios2/boot.c
View File

@ -31,6 +31,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "qemu/option.h"
#include "qemu/config-file.h"
@ -181,7 +182,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
/* Not an ELF image nor an u-boot image, try a RAW image. */
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename, ddr_base,
ram_size);
ramsize);
boot_info.bootstrap_pc = ddr_base;
high = ddr_base + kernel_size;
}
@ -198,11 +199,11 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
initrd_size = load_ramdisk(initrd_filename,
boot_info.initrd_start,
ram_size - initrd_offset);
ramsize - initrd_offset);
if (initrd_size < 0) {
initrd_size = load_image_targphys(initrd_filename,
boot_info.initrd_start,
ram_size - initrd_offset);
ramsize - initrd_offset);
}
if (initrd_size < 0) {
error_report("could not load initrd '%s'",
@ -216,7 +217,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base,
/* Device tree must be placed right after initrd (if available) */
boot_info.fdt = high;
fdt_size = nios2_load_dtb(boot_info, ram_size, kernel_cmdline,
fdt_size = nios2_load_dtb(boot_info, ramsize, kernel_cmdline,
/* Preference a -dtb argument */
dtb_arg ? dtb_arg : filename);
high += fdt_size;

1
hw/nvram/fw_cfg.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "sysemu/sysemu.h"
#include "sysemu/dma.h"
#include "sysemu/reset.h"

1
hw/pci-host/prep.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "hw/pci/pci.h"

1
hw/pci/pci.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"

5
hw/ppc/e500.c
View File

@ -16,6 +16,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "e500.h"
@ -1035,7 +1036,7 @@ void ppce500_init(MachineState *machine)
* -kernel to users but allows them to run through u-boot as well.
*/
kernel_as_payload = false;
if (bios_name == NULL) {
if (machine->firmware == NULL) {
if (machine->kernel_filename) {
payload_name = machine->kernel_filename;
kernel_as_payload = true;
@ -1043,7 +1044,7 @@ void ppce500_init(MachineState *machine)
payload_name = "u-boot.e500";
}
} else {
payload_name = bios_name;
payload_name = machine->firmware;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);

5
hw/ppc/mac_newworld.c
View File

@ -48,6 +48,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/ppc/ppc.h"
#include "hw/qdev-properties.h"
@ -109,6 +110,7 @@ static void ppc_core99_reset(void *opaque)
static void ppc_core99_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *bios_name = machine->firmware ?: PROM_FILENAME;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@ -161,9 +163,6 @@ static void ppc_core99_init(MachineState *machine)
&error_fatal);
memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
if (!bios_name) {
bios_name = PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
/* Load OpenBIOS (ELF) */

5
hw/ppc/mac_oldworld.c
View File

@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "hw/ppc/ppc.h"
@ -83,6 +84,7 @@ static void ppc_heathrow_reset(void *opaque)
static void ppc_heathrow_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *bios_name = machine->firmware ?: PROM_FILENAME;
const char *boot_device = machine->boot_order;
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
@ -130,9 +132,6 @@ static void ppc_heathrow_init(MachineState *machine)
&error_fatal);
memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
if (!bios_name) {
bios_name = PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
/* Load OpenBIOS (ELF) */

6
hw/ppc/pnv.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "sysemu/qtest.h"
@ -713,6 +714,7 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
static void pnv_init(MachineState *machine)
{
const char *bios_name = machine->firmware ?: FW_FILE_NAME;
PnvMachineState *pnv = PNV_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
char *fw_filename;
@ -739,10 +741,6 @@ static void pnv_init(MachineState *machine)
pnv->pnor = PNV_PNOR(dev);
/* load skiboot firmware */
if (bios_name == NULL) {
bios_name = FW_FILE_NAME;
}
fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (!fw_filename) {
error_report("Could not find OPAL firmware '%s'", bios_name);

7
hw/ppc/ppc405_boards.c
View File

@ -26,6 +26,7 @@
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/qdev-properties.h"
@ -141,6 +142,7 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
static void ref405ep_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *bios_name = machine->firmware ?: BIOS_FILENAME;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
@ -206,8 +208,6 @@ static void ref405ep_init(MachineState *machine)
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_size(filename,
@ -425,6 +425,7 @@ static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
static void taihu_405ep_init(MachineState *machine)
{
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *bios_name = machine->firmware ?: BIOS_FILENAME;
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
char *filename;
@ -475,8 +476,6 @@ static void taihu_405ep_init(MachineState *machine)
} else
#endif
{
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
bios = g_new(MemoryRegion, 1);
memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
&error_fatal);

1
hw/ppc/ppc440_bamboo.c
View File

@ -15,6 +15,7 @@
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/error-report.h"
#include "net/net.h"
#include "hw/pci/pci.h"

6
hw/ppc/prep.c
View File

@ -237,6 +237,7 @@ static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
static void ibm_40p_init(MachineState *machine)
{
const char *bios_name = machine->firmware ?: "openbios-ppc";
CPUPPCState *env = NULL;
uint16_t cmos_checksum;
PowerPCCPU *cpu;
@ -271,9 +272,6 @@ static void ibm_40p_init(MachineState *machine)
/* PCI host */
dev = qdev_new("raven-pcihost");
if (!bios_name) {
bios_name = "openbios-ppc";
}
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
pcihost = SYS_BUS_DEVICE(dev);
@ -422,7 +420,7 @@ static void ibm_40p_init(MachineState *machine)
/* Prepare firmware configuration for Open Hack'Ware */
if (m48t59) {
PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
boot_device,
kernel_base, kernel_size,
machine->kernel_cmdline,

1
hw/ppc/sam460ex.c
View File

@ -14,6 +14,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/boards.h"

11
hw/ppc/spapr.c
View File

@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "sysemu/sysemu.h"
@ -2657,6 +2658,7 @@ static void spapr_machine_init(MachineState *machine)
SpaprMachineState *spapr = SPAPR_MACHINE(machine);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *bios_name = machine->firmware ?: FW_FILE_NAME;
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
PCIHostState *phb;
@ -2876,10 +2878,8 @@ static void spapr_machine_init(MachineState *machine)
/* Set up VIO bus */
spapr->vio_bus = spapr_vio_bus_init();
for (i = 0; i < serial_max_hds(); i++) {
if (serial_hd(i)) {
spapr_vty_create(spapr->vio_bus, serial_hd(i));
}
for (i = 0; serial_hd(i); i++) {
spapr_vty_create(spapr->vio_bus, serial_hd(i));
}
/* We always have at least the nvram device on VIO */
@ -2980,9 +2980,6 @@ static void spapr_machine_init(MachineState *machine)
}
}
if (bios_name == NULL) {
bios_name = FW_FILE_NAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (!filename) {
error_report("Could not find LPAR firmware '%s'", bios_name);

4
hw/ppc/spapr_vio.c
View File

@ -525,10 +525,10 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
uint32_t liobn = SPAPR_VIO_LIOBN(dev->reg);
memory_region_init(&dev->mrroot, OBJECT(dev), "iommu-spapr-root",
ram_size);
MACHINE(spapr)->ram_size);
memory_region_init_alias(&dev->mrbypass, OBJECT(dev),
"iommu-spapr-bypass", get_system_memory(),
0, ram_size);
0, MACHINE(spapr)->ram_size);
memory_region_add_subregion_overlap(&dev->mrroot, 0, &dev->mrbypass, 1);
address_space_init(&dev->as, &dev->mrroot, qdev->id);

1
hw/ppc/virtex_ml507.c
View File

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "cpu.h"
#include "hw/sysbus.h"

6
hw/riscv/boot.c
View File

@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "exec/cpu-defs.h"
@ -120,7 +121,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
}
firmware_size = load_image_targphys_as(firmware_filename,
firmware_load_addr, ram_size, NULL);
firmware_load_addr,
current_machine->ram_size, NULL);
if (firmware_size > 0) {
return firmware_load_addr + firmware_size;
@ -148,7 +150,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
}
if (load_image_targphys_as(kernel_filename, kernel_start_addr,
ram_size, NULL) > 0) {
current_machine->ram_size, NULL) > 0) {
return kernel_start_addr;
}

10
hw/rx/rx-gdbsim.c
View File

@ -106,6 +106,16 @@ static void rx_gdbsim_init(MachineState *machine)
rxc->xtal_freq_hz, &error_abort);
object_property_set_bool(OBJECT(&s->mcu), "load-kernel",
kernel_filename != NULL, &error_abort);
if (!kernel_filename) {
if (machine->firmware) {
rom_add_file_fixed(machine->firmware, RX62N_CFLASH_BASE, 0);
} else if (!qtest_enabled()) {
error_report("No bios or kernel specified");
exit(1);
}
}
qdev_realize(DEVICE(&s->mcu), NULL, &error_abort);
/* Load kernel and dtb */

9
hw/rx/rx62n.c
View File

@ -245,15 +245,6 @@ static void rx62n_realize(DeviceState *dev, Error **errp)
rxc->rom_flash_size, &error_abort);
memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash);
if (!s->kernel) {
if (bios_name) {
rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0);
} else if (!qtest_enabled()) {
error_report("No bios or kernel specified");
exit(1);
}
}
/* Initialize CPU */
object_initialize_child(OBJECT(s), "cpu", &s->cpu, TYPE_RX62N_CPU);
qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);

19
hw/s390x/ipl.c
View File

@ -14,6 +14,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@ -112,6 +113,7 @@ static uint64_t bios_translate_addr(void *opaque, uint64_t srcaddr)
static void s390_ipl_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
S390IPLState *ipl = S390_IPL(dev);
uint32_t *ipl_psw;
uint64_t pentry;
@ -126,13 +128,9 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
* even if an external kernel has been defined.
*/
if (!ipl->kernel || ipl->enforce_bios) {
uint64_t fwbase = (MIN(ram_size, 0x80000000U) - 0x200000) & ~0xffffUL;
uint64_t fwbase = (MIN(ms->ram_size, 0x80000000U) - 0x200000) & ~0xffffUL;
if (bios_name == NULL) {
bios_name = ipl->firmware;
}
bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, ipl->firmware);
if (bios_filename == NULL) {
error_setg(errp, "could not find stage1 bootloader");
return;
@ -154,7 +152,7 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
g_free(bios_filename);
if (bios_size == -1) {
error_setg(errp, "could not load bootloader '%s'", bios_name);
error_setg(errp, "could not load bootloader '%s'", ipl->firmware);
return;
}
@ -167,7 +165,7 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
&pentry, NULL,
NULL, NULL, 1, EM_S390, 0, 0);
if (kernel_size < 0) {
kernel_size = load_image_targphys(ipl->kernel, 0, ram_size);
kernel_size = load_image_targphys(ipl->kernel, 0, ms->ram_size);
if (kernel_size < 0) {
error_setg(errp, "could not load kernel '%s'", ipl->kernel);
return;
@ -214,7 +212,7 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)
initrd_offset += 0x100000;
}
initrd_size = load_image_targphys(ipl->initrd, initrd_offset,
ram_size - initrd_offset);
ms->ram_size - initrd_offset);
if (initrd_size == -1) {
error_setg(errp, "could not load initrd '%s'", ipl->initrd);
return;
@ -452,6 +450,7 @@ int s390_ipl_set_loadparm(uint8_t *loadparm)
static int load_netboot_image(Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
S390IPLState *ipl = get_ipl_device();
char *netboot_filename;
MemoryRegion *sysmem = get_system_memory();
@ -484,7 +483,7 @@ static int load_netboot_image(Error **errp)
false);
if (img_size < 0) {
img_size = load_image_size(netboot_filename, ram_ptr, ram_size);
img_size = load_image_size(netboot_filename, ram_ptr, ms->ram_size);
ipl->start_addr = KERN_IMAGE_START;
}

6
hw/s390x/s390-skeys.c
View File

@ -109,7 +109,8 @@ void qmp_dump_skeys(const char *filename, Error **errp)
{
S390SKeysState *ss = s390_get_skeys_device();
S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
const uint64_t total_count = ram_size / TARGET_PAGE_SIZE;
MachineState *ms = MACHINE(qdev_get_machine());
const uint64_t total_count = ms->ram_size / TARGET_PAGE_SIZE;
uint64_t handled_count = 0, cur_count;
Error *lerr = NULL;
vaddr cur_gfn = 0;
@ -256,7 +257,8 @@ static void s390_storage_keys_save(QEMUFile *f, void *opaque)
{
S390SKeysState *ss = S390_SKEYS(opaque);
S390SKeysClass *skeyclass = S390_SKEYS_GET_CLASS(ss);
uint64_t pages_left = ram_size / TARGET_PAGE_SIZE;
MachineState *ms = MACHINE(qdev_get_machine());
uint64_t pages_left = ms->ram_size / TARGET_PAGE_SIZE;
uint64_t read_count, eos = S390_SKEYS_SAVE_FLAG_EOS;
vaddr cur_gfn = 0;
int error = 0;

7
hw/s390x/s390-virtio-ccw.c
View File

@ -17,6 +17,7 @@
#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "exec/ram_addr.h"
#include "hw/boards.h"
#include "hw/s390x/s390-virtio-hcall.h"
#include "hw/s390x/sclp.h"
#include "hw/s390x/s390_flic.h"
@ -142,8 +143,9 @@ static int virtio_ccw_hcall_notify(const uint64_t *args)
static int virtio_ccw_hcall_early_printk(const uint64_t *args)
{
uint64_t mem = args[0];
MachineState *ms = MACHINE(qdev_get_machine());
if (mem < ram_size) {
if (mem < ms->ram_size) {
/* Early printk */
return 0;
}
@ -259,7 +261,8 @@ static void ccw_init(MachineState *machine)
/* get a BUS */
css_bus = virtual_css_bus_init();
s390_init_ipl_dev(machine->kernel_filename, machine->kernel_cmdline,
machine->initrd_filename, "s390-ccw.img",
machine->initrd_filename,
machine->firmware ?: "s390-ccw.img",
"s390-netboot.img", true);
dev = qdev_new(TYPE_S390_PCI_HOST_BRIDGE);

12
hw/sd/ssi-sd.c
View File

@ -42,7 +42,7 @@ typedef enum {
} ssi_sd_mode;
struct ssi_sd_state {
SSISlave ssidev;
SSIPeripheral ssidev;
uint32_t mode;
int cmd;
uint8_t cmdarg[4];
@ -73,7 +73,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
#define SSI_SDR_ADDRESS_ERROR 0x2000
#define SSI_SDR_PARAMETER_ERROR 0x4000
static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
{
ssi_sd_state *s = SSI_SD(dev);
@ -235,12 +235,12 @@ static const VMStateDescription vmstate_ssi_sd = {
VMSTATE_INT32(arglen, ssi_sd_state),
VMSTATE_INT32(response_pos, ssi_sd_state),
VMSTATE_INT32(stopping, ssi_sd_state),
VMSTATE_SSI_SLAVE(ssidev, ssi_sd_state),
VMSTATE_SSI_PERIPHERAL(ssidev, ssi_sd_state),
VMSTATE_END_OF_LIST()
}
};
static void ssi_sd_realize(SSISlave *d, Error **errp)
static void ssi_sd_realize(SSIPeripheral *d, Error **errp)
{
ERRP_GUARD();
ssi_sd_state *s = SSI_SD(d);
@ -291,7 +291,7 @@ static void ssi_sd_reset(DeviceState *dev)
static void ssi_sd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
k->realize = ssi_sd_realize;
k->transfer = ssi_sd_transfer;
@ -304,7 +304,7 @@ static void ssi_sd_class_init(ObjectClass *klass, void *data)
static const TypeInfo ssi_sd_info = {
.name = TYPE_SSI_SD,
.parent = TYPE_SSI_SLAVE,
.parent = TYPE_SSI_PERIPHERAL,
.instance_size = sizeof(ssi_sd_state),
.class_init = ssi_sd_class_init,
};

3
hw/sh4/shix.c
View File

@ -49,6 +49,7 @@ static void shix_init(MachineState *machine)
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
MemoryRegion *sdram = g_new(MemoryRegion, 2);
const char *bios_name = machine->firmware ?: BIOS_FILENAME;
cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
@ -63,8 +64,6 @@ static void shix_init(MachineState *machine)
memory_region_add_subregion(sysmem, 0x0c000000, &sdram[1]);
/* Load BIOS in 0 (and access it through P2, 0xA0000000) */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
ret = load_image_targphys(bios_name, 0, 0x4000);
if (ret < 0 && !qtest_enabled()) {
error_report("Could not load SHIX bios '%s'", bios_name);

8
hw/smbios/smbios.c
View File

@ -678,13 +678,13 @@ static void smbios_build_type_16_table(unsigned dimm_cnt)
t->location = 0x01; /* Other */
t->use = 0x03; /* System memory */
t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */
size_kb = QEMU_ALIGN_UP(ram_size, KiB) / KiB;
size_kb = QEMU_ALIGN_UP(current_machine->ram_size, KiB) / KiB;
if (size_kb < MAX_T16_STD_SZ) {
t->maximum_capacity = cpu_to_le32(size_kb);
t->extended_maximum_capacity = cpu_to_le64(0);
} else {
t->maximum_capacity = cpu_to_le32(MAX_T16_STD_SZ);
t->extended_maximum_capacity = cpu_to_le64(ram_size);
t->extended_maximum_capacity = cpu_to_le64(current_machine->ram_size);
}
t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
t->number_of_memory_devices = cpu_to_le16(dimm_cnt);
@ -911,9 +911,9 @@ void smbios_get_tables(MachineState *ms,
#define MAX_DIMM_SZ (16 * GiB)
#define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \
: ((ram_size - 1) % MAX_DIMM_SZ) + 1)
: ((current_machine->ram_size - 1) % MAX_DIMM_SZ) + 1)
dimm_cnt = QEMU_ALIGN_UP(ram_size, MAX_DIMM_SZ) / MAX_DIMM_SZ;
dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ) / MAX_DIMM_SZ;
smbios_build_type_16_table(dimm_cnt);

5
hw/sparc/leon3.c
View File

@ -27,6 +27,7 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/irq.h"
#include "qemu/timer.h"
@ -185,6 +186,7 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
static void leon3_generic_hw_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *bios_name = machine->firmware ?: LEON3_PROM_FILENAME;
const char *kernel_filename = machine->kernel_filename;
SPARCCPU *cpu;
CPUSPARCState *env;
@ -259,9 +261,6 @@ static void leon3_generic_hw_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
/* Load boot prom */
if (bios_name == NULL) {
bios_name = LEON3_PROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {

3
hw/sparc/sun4m.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
@ -882,7 +883,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
hwdef->max_mem - machine->ram_size);
}
prom_init(hwdef->slavio_base, bios_name);
prom_init(hwdef->slavio_base, machine->firmware);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,

3
hw/sparc64/sparc64.c
View File

@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/boards.h"
#include "hw/char/serial.h"
#include "hw/sparc/sparc64.h"
#include "qemu/timer.h"
@ -180,7 +181,7 @@ static void main_cpu_reset(void *opaque)
cpu_timer_reset(env->hstick);
env->gregs[1] = 0; /* Memory start */
env->gregs[2] = ram_size; /* Memory size */
env->gregs[2] = current_machine->ram_size; /* Memory size */
env->gregs[3] = 0; /* Machine description XXX */
if (nr_resets++ == 0) {
/* Power on reset */

7
hw/sparc64/sun4u.c
View File

@ -27,6 +27,7 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
@ -578,7 +579,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
prom_init(hwdef->prom_addr, machine->firmware);
/* Init sabre (PCI host bridge) */
sabre = SABRE(qdev_new(TYPE_SABRE));
@ -690,7 +691,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
initrd_addr = 0;
kernel_size = sun4u_load_kernel(machine->kernel_filename,
machine->initrd_filename,
ram_size, &initrd_size, &initrd_addr,
machine->ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
@ -713,7 +714,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
fw_cfg = FW_CFG(dev);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);

53
hw/ssi/aspeed_smc.c
View File

@ -191,7 +191,7 @@
#define SNOOP_START 0x0
/*
* Default segments mapping addresses and size for each slave per
* Default segments mapping addresses and size for each peripheral per
* controller. These can be changed when board is initialized with the
* Segment Address Registers.
*/
@ -269,7 +269,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 1,
.max_peripherals = 1,
.segments = aspeed_segments_legacy,
.flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
.flash_window_size = 0x6000000,
@ -285,7 +285,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 5,
.max_peripherals = 5,
.segments = aspeed_segments_fmc,
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
@ -303,7 +303,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_SPI_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = SPI_CONF_ENABLE_W0,
.max_slaves = 1,
.max_peripherals = 1,
.segments = aspeed_segments_spi,
.flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
.flash_window_size = 0x10000000,
@ -319,7 +319,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 3,
.max_peripherals = 3,
.segments = aspeed_segments_ast2500_fmc,
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
@ -337,7 +337,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 2,
.max_peripherals = 2,
.segments = aspeed_segments_ast2500_spi1,
.flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
.flash_window_size = 0x8000000,
@ -353,7 +353,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 2,
.max_peripherals = 2,
.segments = aspeed_segments_ast2500_spi2,
.flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
.flash_window_size = 0x8000000,
@ -369,7 +369,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 3,
.max_peripherals = 3,
.segments = aspeed_segments_ast2600_fmc,
.flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
@ -387,7 +387,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 2,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 2,
.max_peripherals = 2,
.segments = aspeed_segments_ast2600_spi1,
.flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
.flash_window_size = 0x10000000,
@ -405,7 +405,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 3,
.conf_enable_w0 = CONF_ENABLE_W0,
.max_slaves = 3,
.max_peripherals = 3,
.segments = aspeed_segments_ast2600_spi2,
.flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
.flash_window_size = 0x10000000,
@ -420,7 +420,7 @@ static const AspeedSMCController controllers[] = {
/*
* The Segment Registers of the AST2400 and AST2500 have a 8MB
* unit. The address range of a flash SPI slave is encoded with
* unit. The address range of a flash SPI peripheral is encoded with
* absolute addresses which should be part of the overall controller
* window.
*/
@ -442,7 +442,7 @@ static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
/*
* The Segment Registers of the AST2600 have a 1MB unit. The address
* range of a flash SPI slave is encoded with offsets in the overall
* range of a flash SPI peripheral is encoded with offsets in the overall
* controller window. The previous SoC AST2400 and AST2500 used
* absolute addresses. Only bits [27:20] are relevant and the end
* address is an upper bound limit.
@ -486,7 +486,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
AspeedSegments seg;
int i;
for (i = 0; i < s->ctrl->max_slaves; i++) {
for (i = 0; i < s->ctrl->max_peripherals; i++) {
if (i == cs) {
continue;
}
@ -547,7 +547,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
*/
if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
cs == s->ctrl->max_slaves &&
cs == s->ctrl->max_peripherals &&
seg.addr + seg.size != s->ctrl->segments[cs].addr +
s->ctrl->segments[cs].size) {
qemu_log_mask(LOG_GUEST_ERROR,
@ -949,14 +949,14 @@ static void aspeed_smc_reset(DeviceState *d)
memset(s->regs, 0, sizeof s->regs);
/* Unselect all slaves */
/* Unselect all peripherals */
for (i = 0; i < s->num_cs; ++i) {
s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
qemu_set_irq(s->cs_lines[i], true);
}
/* setup the default segment register values and regions for all */
for (i = 0; i < s->ctrl->max_slaves; ++i) {
for (i = 0; i < s->ctrl->max_peripherals; ++i) {
aspeed_smc_flash_set_segment_region(s, i,
s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]));
}
@ -1004,8 +1004,9 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
(s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
(s->ctrl->has_dma && addr == R_DMA_LEN) ||
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
(addr >= R_SEG_ADDR0 &&
addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) ||
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_peripherals)) {
trace_aspeed_smc_read(addr, size, s->regs[addr]);
@ -1279,7 +1280,7 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
int cs = addr - s->r_ctrl0;
aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
} else if (addr >= R_SEG_ADDR0 &&
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) {
int cs = addr - R_SEG_ADDR0;
if (value != s->regs[R_SEG_ADDR0 + cs]) {
@ -1352,10 +1353,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
s->conf_enable_w0 = s->ctrl->conf_enable_w0;
/* Enforce some real HW limits */
if (s->num_cs > s->ctrl->max_slaves) {
if (s->num_cs > s->ctrl->max_peripherals) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
__func__, s->ctrl->max_slaves);
s->num_cs = s->ctrl->max_slaves;
__func__, s->ctrl->max_peripherals);
s->num_cs = s->ctrl->max_peripherals;
}
/* DMA irq. Keep it first for the initialization in the SoC */
@ -1363,7 +1364,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
s->spi = ssi_create_bus(dev, "spi");
/* Setup cs_lines for slaves */
/* Setup cs_lines for peripherals */
s->cs_lines = g_new0(qemu_irq, s->num_cs);
for (i = 0; i < s->num_cs; ++i) {
@ -1387,16 +1388,16 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
s->ctrl->flash_window_size);
sysbus_init_mmio(sbd, &s->mmio_flash);
s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_peripherals);
/*
* Let's create a sub memory region for each possible slave. All
* Let's create a sub memory region for each possible peripheral. All
* have a configurable memory segment in the overall flash mapping
* window of the controller but, there is not necessarily a flash
* module behind to handle the memory accesses. This depends on
* the board configuration.
*/
for (i = 0; i < s->ctrl->max_slaves; ++i) {
for (i = 0; i < s->ctrl->max_peripherals; ++i) {
AspeedSMCFlash *fl = &s->flashes[i];
snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);

2
hw/ssi/pl022.c
View File

@ -174,7 +174,7 @@ static void pl022_write(void *opaque, hwaddr offset,
s->cr1 = value;
if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE))
== (PL022_CR1_MS | PL022_CR1_SSE)) {
BADF("SPI slave mode not implemented\n");
BADF("SPI peripheral mode not implemented\n");
}
pl022_xfer(s);
break;

48
hw/ssi/ssi.c
View File

@ -34,11 +34,11 @@ static const TypeInfo ssi_bus_info = {
static void ssi_cs_default(void *opaque, int n, int level)
{
SSISlave *s = SSI_SLAVE(opaque);
SSIPeripheral *s = SSI_PERIPHERAL(opaque);
bool cs = !!level;
assert(n == 0);
if (s->cs != cs) {
SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
if (ssc->set_cs) {
ssc->set_cs(s, cs);
}
@ -46,9 +46,9 @@ static void ssi_cs_default(void *opaque, int n, int level)
s->cs = cs;
}
static uint32_t ssi_transfer_raw_default(SSISlave *dev, uint32_t val)
static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
{
SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(dev);
SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(dev);
if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
(!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
@ -58,10 +58,10 @@ static uint32_t ssi_transfer_raw_default(SSISlave *dev, uint32_t val)
return 0;
}
static void ssi_slave_realize(DeviceState *dev, Error **errp)
static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
{
SSISlave *s = SSI_SLAVE(dev);
SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
SSIPeripheral *s = SSI_PERIPHERAL(dev);
SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
if (ssc->transfer_raw == ssi_transfer_raw_default &&
ssc->cs_polarity != SSI_CS_NONE) {
@ -71,23 +71,23 @@ static void ssi_slave_realize(DeviceState *dev, Error **errp)
ssc->realize(s, errp);
}
static void ssi_slave_class_init(ObjectClass *klass, void *data)
static void ssi_peripheral_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *ssc = SSI_SLAVE_CLASS(klass);
SSIPeripheralClass *ssc = SSI_PERIPHERAL_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ssi_slave_realize;
dc->realize = ssi_peripheral_realize;
dc->bus_type = TYPE_SSI_BUS;
if (!ssc->transfer_raw) {
ssc->transfer_raw = ssi_transfer_raw_default;
}
}
static const TypeInfo ssi_slave_info = {
.name = TYPE_SSI_SLAVE,
static const TypeInfo ssi_peripheral_info = {
.name = TYPE_SSI_PERIPHERAL,
.parent = TYPE_DEVICE,
.class_init = ssi_slave_class_init,
.class_size = sizeof(SSISlaveClass),
.class_init = ssi_peripheral_class_init,
.class_size = sizeof(SSIPeripheralClass),
.abstract = true,
};
@ -96,7 +96,7 @@ bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
}
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name)
{
DeviceState *dev = qdev_new(name);
@ -115,32 +115,32 @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
{
BusState *b = BUS(bus);
BusChild *kid;
SSISlaveClass *ssc;
SSIPeripheralClass *ssc;
uint32_t r = 0;
QTAILQ_FOREACH(kid, &b->children, sibling) {
SSISlave *slave = SSI_SLAVE(kid->child);
ssc = SSI_SLAVE_GET_CLASS(slave);
r |= ssc->transfer_raw(slave, val);
SSIPeripheral *peripheral = SSI_PERIPHERAL(kid->child);
ssc = SSI_PERIPHERAL_GET_CLASS(peripheral);
r |= ssc->transfer_raw(peripheral, val);
}
return r;
}
const VMStateDescription vmstate_ssi_slave = {
const VMStateDescription vmstate_ssi_peripheral = {
.name = "SSISlave",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_BOOL(cs, SSISlave),
VMSTATE_BOOL(cs, SSIPeripheral),
VMSTATE_END_OF_LIST()
}
};
static void ssi_slave_register_types(void)
static void ssi_peripheral_register_types(void)
{
type_register_static(&ssi_bus_info);
type_register_static(&ssi_slave_info);
type_register_static(&ssi_peripheral_info);
}
type_init(ssi_slave_register_types)
type_init(ssi_peripheral_register_types)

9
hw/ssi/xilinx_spips.c
View File

@ -236,7 +236,8 @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
if (old_state != new_state) {
s->cs_lines_state[i] = new_state;
s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD);
DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i);
DB_PRINT_L(1, "%sselecting peripheral %d\n",
new_state ? "" : "de", i);
}
qemu_set_irq(s->cs_lines[i], !new_state);
}
@ -1154,7 +1155,7 @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
int i;
int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1))
/ num_effective_busses(s));
int slave = flash_addr >> LQSPI_ADDRESS_BITS;
int peripheral = flash_addr >> LQSPI_ADDRESS_BITS;
int cache_entry = 0;
uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
@ -1162,7 +1163,7 @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
xilinx_qspips_invalidate_mmio_ptr(q);
s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
s->regs[R_LQSPI_STS] |= peripheral ? LQSPI_CFG_U_PAGE : 0;
DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
@ -1353,7 +1354,7 @@ static void xlnx_zynqmp_qspips_init(Object *obj)
{
XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK,
(Object **)&rq->dma,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);

3
hw/virtio/virtio-balloon.c
View File

@ -20,6 +20,7 @@
#include "hw/virtio/virtio.h"
#include "hw/mem/pc-dimm.h"
#include "hw/qdev-properties.h"
#include "hw/boards.h"
#include "sysemu/balloon.h"
#include "hw/virtio/virtio-balloon.h"
#include "exec/address-spaces.h"
@ -748,7 +749,7 @@ static int build_dimm_list(Object *obj, void *opaque)
static ram_addr_t get_current_ram_size(void)
{
GSList *list = NULL, *item;
ram_addr_t size = ram_size;
ram_addr_t size = current_machine->ram_size;
build_dimm_list(qdev_get_machine(), &list);
for (item = list; item; item = g_slist_next(item)) {

2
include/exec/cpu-common.h
View File

@ -42,8 +42,6 @@ typedef uintptr_t ram_addr_t;
# define RAM_ADDR_FMT "%" PRIxPTR
#endif
extern ram_addr_t ram_size;
/* memory API */
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);

2
include/hw/boards.h
View File

@ -26,6 +26,7 @@ OBJECT_DECLARE_TYPE(MachineState, MachineClass, MACHINE)
extern MachineState *current_machine;
void machine_run_board_init(MachineState *machine);
bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp);
bool machine_usb(MachineState *machine);
int machine_phandle_start(MachineState *machine);
bool machine_dump_guest_core(MachineState *machine);
@ -282,6 +283,7 @@ struct MachineState {
ram_addr_t maxram_size;
uint64_t ram_slots;
const char *boot_order;
const char *boot_once;
char *kernel_filename;
char *kernel_cmdline;
char *initrd_filename;

3
include/hw/i386/x86.h
View File

@ -102,7 +102,8 @@ void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp);
void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
MemoryRegion *rom_memory, bool isapc_ram_fw);
void x86_load_linux(X86MachineState *x86ms,
FWCfgState *fw_cfg,

2
include/hw/misc/max111x.h
View File

@ -33,7 +33,7 @@
* be lowered once it has been asserted.
*/
struct MAX111xState {
SSISlave parent_obj;
SSIPeripheral parent_obj;
qemu_irq interrupt;
/* Values of inputs at system reset (settable by QOM property) */

50
include/hw/pci/pci.h
View File

@ -781,20 +781,58 @@ static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
return &dev->bus_master_as;
}
static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len, DMADirection dir)
/**
* pci_dma_rw: Read from or write to an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to read or write
* @dir: indicates the transfer direction
*/
static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len,
DMADirection dir)
{
return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
}
static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len)
/**
* pci_dma_read: Read from an address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault). Called within RCU critical section.
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: length of the data transferred
*/
static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
}
static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
const void *buf, dma_addr_t len)
/**
* pci_dma_write: Write to address space from PCI device.
*
* Return a MemTxResult indicating whether the operation succeeded
* or failed (eg unassigned memory, device rejected the transaction,
* IOMMU fault).
*
* @dev: #PCIDevice doing the memory access
* @addr: address within the #PCIDevice address space
* @buf: buffer with the data transferred
* @len: the number of bytes to write
*/
static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
const void *buf, dma_addr_t len)
{
return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
}

8
include/hw/qdev-core.h
View File

@ -787,14 +787,6 @@ BusState *sysbus_get_default(void);
char *qdev_get_fw_dev_path(DeviceState *dev);
char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev);
/**
* @qdev_machine_init
*
* Initialize platform devices before machine init. This is a hack until full
* support for composition is added.
*/
void qdev_machine_init(void);
/**
* device_legacy_reset:
*

2
include/hw/ssi/aspeed_smc.h
View File

@ -43,7 +43,7 @@ typedef struct AspeedSMCController {
uint8_t r_timings;
uint8_t nregs_timings;
uint8_t conf_enable_w0;
uint8_t max_slaves;
uint8_t max_peripherals;
const AspeedSegments *segments;
hwaddr flash_window_base;
uint32_t flash_window_size;

56
include/hw/ssi/ssi.h
View File

@ -1,12 +1,14 @@
/* QEMU Synchronous Serial Interface support. */
/* In principle SSI is a point-point interface. As such the qemu
implementation has a single slave device on a "bus".
However it is fairly common for boards to have multiple slaves
connected to a single master, and select devices with an external
chip select. This is implemented in qemu by having an explicit mux device.
It is assumed that master and slave are both using the same transfer width.
*/
/*
* In principle SSI is a point-point interface. As such the qemu
* implementation has a single peripheral on a "bus".
* However it is fairly common for boards to have multiple peripherals
* connected to a single master, and select devices with an external
* chip select. This is implemented in qemu by having an explicit mux device.
* It is assumed that master and peripheral are both using the same transfer
* width.
*/
#ifndef QEMU_SSI_H
#define QEMU_SSI_H
@ -16,9 +18,9 @@
typedef enum SSICSMode SSICSMode;
#define TYPE_SSI_SLAVE "ssi-slave"
OBJECT_DECLARE_TYPE(SSISlave, SSISlaveClass,
SSI_SLAVE)
#define TYPE_SSI_PERIPHERAL "ssi-peripheral"
OBJECT_DECLARE_TYPE(SSIPeripheral, SSIPeripheralClass,
SSI_PERIPHERAL)
#define SSI_GPIO_CS "ssi-gpio-cs"
@ -28,21 +30,21 @@ enum SSICSMode {
SSI_CS_HIGH,
};
/* Slave devices. */
struct SSISlaveClass {
/* Peripherals. */
struct SSIPeripheralClass {
DeviceClass parent_class;
void (*realize)(SSISlave *dev, Error **errp);
void (*realize)(SSIPeripheral *dev, Error **errp);
/* if you have standard or no CS behaviour, just override transfer.
* This is called when the device cs is active (true by default).
*/
uint32_t (*transfer)(SSISlave *dev, uint32_t val);
uint32_t (*transfer)(SSIPeripheral *dev, uint32_t val);
/* called when the CS line changes. Optional, devices only need to implement
* this if they have side effects associated with the cs line (beyond
* tristating the txrx lines).
*/
int (*set_cs)(SSISlave *dev, bool select);
int (*set_cs)(SSIPeripheral *dev, bool select);
/* define whether or not CS exists and is active low/high */
SSICSMode cs_polarity;
@ -51,30 +53,30 @@ struct SSISlaveClass {
* cs_polarity are unused if this is overwritten. Transfer_raw will
* always be called for the device for every txrx access to the parent bus
*/
uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
uint32_t (*transfer_raw)(SSIPeripheral *dev, uint32_t val);
};
struct SSISlave {
struct SSIPeripheral {
DeviceState parent_obj;
/* Chip select state */
bool cs;
};
extern const VMStateDescription vmstate_ssi_slave;
extern const VMStateDescription vmstate_ssi_peripheral;
#define VMSTATE_SSI_SLAVE(_field, _state) { \
#define VMSTATE_SSI_PERIPHERAL(_field, _state) { \
.name = (stringify(_field)), \
.size = sizeof(SSISlave), \
.vmsd = &vmstate_ssi_slave, \
.size = sizeof(SSIPeripheral), \
.vmsd = &vmstate_ssi_peripheral, \
.flags = VMS_STRUCT, \
.offset = vmstate_offset_value(_state, _field, SSISlave), \
.offset = vmstate_offset_value(_state, _field, SSIPeripheral), \
}
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name);
/**
* ssi_realize_and_unref: realize and unref an SSI slave device
* @dev: SSI slave device to realize
* ssi_realize_and_unref: realize and unref an SSI peripheral
* @dev: SSI peripheral to realize
* @bus: SSI bus to put it on
* @errp: error pointer
*
@ -85,10 +87,10 @@ DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
* This function is useful if you have created @dev via qdev_new()
* (which takes a reference to the device it returns to you), so that
* you can set properties on it before realizing it. If you don't need
* to set properties then ssi_create_slave() is probably better (as it
* to set properties then ssi_create_peripheral() is probably better (as it
* does the create, init and realize in one step).
*
* If you are embedding the SSI slave into another QOM device and
* If you are embedding the SSI peripheral into another QOM device and
* initialized it via some variant on object_initialize_child() then
* do not use this function, because that family of functions arrange
* for the only reference to the child device to be held by the parent

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