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arm: add dummy gic security registers

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Implement handling for the RAZ/WI gic security registers.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rob Herring 2011-12-29 06:19:53 +00:00 committed by Peter Maydell
parent 104a26a236
commit b79f22656f
1 changed files with 6 additions and 0 deletions
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6
hw/arm_gic.c
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@ -282,6 +282,10 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
if (offset < 0x08)
return 0;
if (offset >= 0x80) {
/* Interrupt Security , RAZ/WI */
return 0;
}
#endif
goto bad_reg;
} else if (offset < 0x200) {
@ -413,6 +417,8 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
} else if (offset < 4) {
/* ignored. */
} else if (offset >= 0x80) {
/* Interrupt Security Registers, RAZ/WI */
} else {
goto bad_reg;
}