target-alpha: Implement the typhoon iommu
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
b114b68adf
commit
b83c4db895
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@ -26,9 +26,9 @@ typedef struct TyphoonCchip {
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} TyphoonCchip;
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typedef struct TyphoonWindow {
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uint32_t base_addr;
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uint32_t mask;
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uint32_t translated_base_pfn;
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uint64_t wba;
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uint64_t wsm;
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uint64_t tba;
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} TyphoonWindow;
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typedef struct TyphoonPchip {
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@ -37,6 +37,10 @@ typedef struct TyphoonPchip {
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MemoryRegion reg_mem;
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MemoryRegion reg_io;
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MemoryRegion reg_conf;
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AddressSpace iommu_as;
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MemoryRegion iommu;
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uint64_t ctl;
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TyphoonWindow win[4];
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} TyphoonPchip;
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@ -209,53 +213,53 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
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switch (addr) {
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case 0x0000:
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/* WSBA0: Window Space Base Address Register. */
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ret = s->pchip.win[0].base_addr;
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ret = s->pchip.win[0].wba;
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break;
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case 0x0040:
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/* WSBA1 */
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ret = s->pchip.win[1].base_addr;
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ret = s->pchip.win[1].wba;
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break;
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case 0x0080:
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/* WSBA2 */
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ret = s->pchip.win[2].base_addr;
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ret = s->pchip.win[2].wba;
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break;
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case 0x00c0:
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/* WSBA3 */
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ret = s->pchip.win[3].base_addr;
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ret = s->pchip.win[3].wba;
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break;
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case 0x0100:
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/* WSM0: Window Space Mask Register. */
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ret = s->pchip.win[0].mask;
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ret = s->pchip.win[0].wsm;
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break;
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case 0x0140:
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/* WSM1 */
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ret = s->pchip.win[1].mask;
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ret = s->pchip.win[1].wsm;
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break;
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case 0x0180:
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/* WSM2 */
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ret = s->pchip.win[2].mask;
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ret = s->pchip.win[2].wsm;
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break;
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case 0x01c0:
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/* WSM3 */
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ret = s->pchip.win[3].mask;
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ret = s->pchip.win[3].wsm;
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break;
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case 0x0200:
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/* TBA0: Translated Base Address Register. */
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ret = (uint64_t)s->pchip.win[0].translated_base_pfn << 10;
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ret = s->pchip.win[0].tba;
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break;
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case 0x0240:
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/* TBA1 */
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ret = (uint64_t)s->pchip.win[1].translated_base_pfn << 10;
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ret = s->pchip.win[1].tba;
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break;
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case 0x0280:
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/* TBA2 */
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ret = (uint64_t)s->pchip.win[2].translated_base_pfn << 10;
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ret = s->pchip.win[2].tba;
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break;
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case 0x02c0:
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/* TBA3 */
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ret = (uint64_t)s->pchip.win[3].translated_base_pfn << 10;
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ret = s->pchip.win[3].tba;
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break;
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case 0x0300:
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@ -458,53 +462,53 @@ static void pchip_write(void *opaque, hwaddr addr,
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switch (addr) {
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case 0x0000:
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/* WSBA0: Window Space Base Address Register. */
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s->pchip.win[0].base_addr = val;
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s->pchip.win[0].wba = val & 0xfff00003u;
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break;
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case 0x0040:
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/* WSBA1 */
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s->pchip.win[1].base_addr = val;
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s->pchip.win[1].wba = val & 0xfff00003u;
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break;
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case 0x0080:
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/* WSBA2 */
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s->pchip.win[2].base_addr = val;
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s->pchip.win[2].wba = val & 0xfff00003u;
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break;
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case 0x00c0:
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/* WSBA3 */
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s->pchip.win[3].base_addr = val;
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s->pchip.win[3].wba = (val & 0x80fff00001ull) | 2;
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break;
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case 0x0100:
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/* WSM0: Window Space Mask Register. */
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s->pchip.win[0].mask = val;
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s->pchip.win[0].wsm = val & 0xfff00000u;
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break;
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case 0x0140:
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/* WSM1 */
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s->pchip.win[1].mask = val;
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s->pchip.win[1].wsm = val & 0xfff00000u;
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break;
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case 0x0180:
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/* WSM2 */
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s->pchip.win[2].mask = val;
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s->pchip.win[2].wsm = val & 0xfff00000u;
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break;
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case 0x01c0:
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/* WSM3 */
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s->pchip.win[3].mask = val;
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s->pchip.win[3].wsm = val & 0xfff00000u;
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break;
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case 0x0200:
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/* TBA0: Translated Base Address Register. */
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s->pchip.win[0].translated_base_pfn = val >> 10;
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s->pchip.win[0].tba = val & 0x7fffffc00ull;
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break;
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case 0x0240:
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/* TBA1 */
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s->pchip.win[1].translated_base_pfn = val >> 10;
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s->pchip.win[1].tba = val & 0x7fffffc00ull;
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break;
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case 0x0280:
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/* TBA2 */
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s->pchip.win[2].translated_base_pfn = val >> 10;
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s->pchip.win[2].tba = val & 0x7fffffc00ull;
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break;
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case 0x02c0:
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/* TBA3 */
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s->pchip.win[3].translated_base_pfn = val >> 10;
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s->pchip.win[3].tba = val & 0x7fffffc00ull;
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break;
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case 0x0300:
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@ -512,7 +516,6 @@ static void pchip_write(void *opaque, hwaddr addr,
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oldval = s->pchip.ctl;
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oldval &= ~0x00001cff0fc7ffull; /* RW fields */
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oldval |= val & 0x00001cff0fc7ffull;
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s->pchip.ctl = oldval;
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break;
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@ -593,6 +596,140 @@ static const MemoryRegionOps pchip_ops = {
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},
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};
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/* A subroutine of typhoon_translate_iommu that builds an IOMMUTLBEntry
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using the given translated address and mask. */
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static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask, IOMMUTLBEntry *ret)
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{
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*ret = (IOMMUTLBEntry) {
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.target_as = &address_space_memory,
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.translated_addr = taddr,
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.addr_mask = mask,
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.perm = IOMMU_RW,
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};
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return true;
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}
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/* A subroutine of typhoon_translate_iommu that handles scatter-gather
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translation, given the address of the PTE. */
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static bool pte_translate(hwaddr pte_addr, IOMMUTLBEntry *ret)
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{
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uint64_t pte = ldq_phys(pte_addr);
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/* Check valid bit. */
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if ((pte & 1) == 0) {
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return false;
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}
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return make_iommu_tlbe((pte & 0x3ffffe) << 12, 0x1fff, ret);
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}
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/* A subroutine of typhoon_translate_iommu that handles one of the
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four single-address-cycle translation windows. */
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static bool window_translate(TyphoonWindow *win, hwaddr addr,
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IOMMUTLBEntry *ret)
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{
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uint32_t wba = win->wba;
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uint64_t wsm = win->wsm;
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uint64_t tba = win->tba;
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uint64_t wsm_ext = wsm | 0xfffff;
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/* Check for window disabled. */
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if ((wba & 1) == 0) {
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return false;
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}
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/* Check for window hit. */
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if ((addr & ~wsm_ext) != (wba & 0xfff00000u)) {
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return false;
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}
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if (wba & 2) {
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/* Scatter-gather translation. */
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hwaddr pte_addr;
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/* See table 10-6, Generating PTE address for PCI DMA Address. */
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pte_addr = tba & ~(wsm >> 10);
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pte_addr |= (addr & (wsm | 0xfe000)) >> 10;
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return pte_translate(pte_addr, ret);
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} else {
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/* Direct-mapped translation. */
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return make_iommu_tlbe(tba & ~wsm_ext, wsm_ext, ret);
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}
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}
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/* Handle PCI-to-system address translation. */
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/* TODO: A translation failure here ought to set PCI error codes on the
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Pchip and generate a machine check interrupt. */
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static IOMMUTLBEntry typhoon_translate_iommu(MemoryRegion *iommu, hwaddr addr)
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{
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TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu);
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IOMMUTLBEntry ret;
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int i;
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if (addr <= 0xffffffffu) {
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/* Single-address cycle. */
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/* Check for the Window Hole, inhibiting matching. */
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if ((pchip->ctl & 0x20)
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&& addr >= 0x80000
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&& addr <= 0xfffff) {
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goto failure;
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}
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/* Check the first three windows. */
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for (i = 0; i < 3; ++i) {
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if (window_translate(&pchip->win[i], addr, &ret)) {
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goto success;
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}
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}
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/* Check the fourth window for DAC disable. */
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if ((pchip->win[3].wba & 0x80000000000ull) == 0
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&& window_translate(&pchip->win[3], addr, &ret)) {
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goto success;
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}
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} else {
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/* Double-address cycle. */
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if (addr >= 0x10000000000ull && addr < 0x20000000000ull) {
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/* Check for the DMA monster window. */
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if (pchip->ctl & 0x40) {
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/* See 10.1.4.4; in particular <39:35> is ignored. */
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make_iommu_tlbe(0, 0x007ffffffffull, &ret);
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goto success;
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}
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}
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if (addr >= 0x80000000000 && addr <= 0xfffffffffff) {
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/* Check the fourth window for DAC enable and window enable. */
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if ((pchip->win[3].wba & 0x80000000001ull) == 0x80000000001ull) {
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uint64_t pte_addr;
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pte_addr = pchip->win[3].tba & 0x7ffc00000ull;
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pte_addr |= (addr & 0xffffe000u) >> 10;
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if (pte_translate(pte_addr, &ret)) {
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goto success;
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}
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}
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}
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}
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failure:
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ret = (IOMMUTLBEntry) { .perm = IOMMU_NONE };
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success:
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return ret;
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}
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static const MemoryRegionIOMMUOps typhoon_iommu_ops = {
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.translate = typhoon_translate_iommu,
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};
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static AddressSpace *typhoon_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
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{
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TyphoonState *s = opaque;
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return &s->pchip.iommu_as;
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}
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static void typhoon_set_irq(void *opaque, int irq, int level)
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{
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TyphoonState *s = opaque;
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@ -688,6 +825,9 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
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s = TYPHOON_PCI_HOST_BRIDGE(dev);
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phb = PCI_HOST_BRIDGE(dev);
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s->cchip.misc = 0x800000000ull; /* Revision: Typhoon. */
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s->pchip.win[3].wba = 2; /* Window 3 SG always enabled. */
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/* Remember the CPUs so that we can deliver interrupts to them. */
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for (i = 0; i < 4; i++) {
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AlphaCPU *cpu = cpus[i];
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@ -746,6 +886,12 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
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0, 64, TYPE_PCI_BUS);
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phb->bus = b;
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/* Host memory as seen from the PCI side, via the IOMMU. */
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memory_region_init_iommu(&s->pchip.iommu, OBJECT(s), &typhoon_iommu_ops,
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"iommu-typhoon", UINT64_MAX);
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address_space_init(&s->pchip.iommu_as, &s->pchip.iommu, "pchip0-pci");
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pci_setup_iommu(b, typhoon_pci_dma_iommu, s);
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/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
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memory_region_init_io(&s->pchip.reg_iack, OBJECT(s), &alpha_pci_iack_ops,
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b, "pci0-iack", 64*MB);
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