Make accesses with wrong width also work as apparently real hardware allows them when the fault is disabled.
Fix DMA register writes if target_phys_addr_t is 64-bit. Make more functions static. A timer hack to make PalmOS run in finite time (uses very short timer periods, much shorter than clocksource tick). Re-calculate internal clock rates on start-up. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3527 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
e616a7e821
commit
b854bc196f
60
hw/omap.c
60
hw/omap.c
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@ -27,38 +27,51 @@ uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
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uint8_t ret;
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OMAP_8B_REG(addr);
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cpu_physical_memory_read(addr, &ret, 1);
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cpu_physical_memory_read(addr, (void *) &ret, 1);
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return ret;
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}
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void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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uint8_t val8 = value;
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OMAP_8B_REG(addr);
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cpu_physical_memory_write(addr, (void *) &val8, 1);
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}
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uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
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{
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uint16_t ret;
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OMAP_16B_REG(addr);
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return 0;
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cpu_physical_memory_read(addr, (void *) &ret, 2);
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return ret;
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}
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void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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uint16_t val16 = value;
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OMAP_16B_REG(addr);
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cpu_physical_memory_write(addr, (void *) &val16, 2);
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}
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uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret;
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OMAP_32B_REG(addr);
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return 0;
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cpu_physical_memory_read(addr, (void *) &ret, 4);
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return ret;
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}
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void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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OMAP_32B_REG(addr);
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cpu_physical_memory_write(addr, (void *) &value, 4);
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}
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/* Interrupt Handlers */
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@ -787,7 +800,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
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case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
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s->ch[ch].addr[0] &= 0x0000ffff;
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s->ch[ch].addr[0] |= value << 16;
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s->ch[ch].addr[0] |= (uint32_t) value << 16;
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break;
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case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
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@ -797,7 +810,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
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case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
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s->ch[ch].addr[1] &= 0x0000ffff;
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s->ch[ch].addr[1] |= value << 16;
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s->ch[ch].addr[1] |= (uint32_t) value << 16;
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break;
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case 0x10: /* SYS_DMA_CEN_CH0 */
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@ -1033,37 +1046,37 @@ struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
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}
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/* DMA ports */
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int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
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static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
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target_phys_addr_t addr)
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{
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return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
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}
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int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
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static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
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target_phys_addr_t addr)
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{
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return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
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}
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int omap_validate_imif_addr(struct omap_mpu_state_s *s,
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static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
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target_phys_addr_t addr)
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{
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return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
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}
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int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
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static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
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target_phys_addr_t addr)
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{
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return addr >= 0xfffb0000 && addr < 0xffff0000;
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}
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int omap_validate_local_addr(struct omap_mpu_state_s *s,
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static int omap_validate_local_addr(struct omap_mpu_state_s *s,
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target_phys_addr_t addr)
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{
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return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
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}
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int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
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static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
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target_phys_addr_t addr)
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{
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return addr >= 0xe1010000 && addr < 0xe1020004;
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@ -1110,9 +1123,23 @@ static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
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if (timer->enable && timer->st && timer->rate) {
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timer->val = timer->reset_val; /* Should skip this on clk enable */
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expires = timer->time + muldiv64(timer->val << (timer->ptv + 1),
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expires = muldiv64(timer->val << (timer->ptv + 1),
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ticks_per_sec, timer->rate);
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qemu_mod_timer(timer->timer, expires);
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/* If timer expiry would be sooner than in about 1 ms and
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* auto-reload isn't set, then fire immediately. This is a hack
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* to make systems like PalmOS run in acceptable time. PalmOS
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* sets the interval to a very low value and polls the status bit
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* in a busy loop when it wants to sleep just a couple of CPU
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* ticks. */
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if (expires > (ticks_per_sec >> 10) || timer->ar)
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qemu_mod_timer(timer->timer, timer->time + expires);
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else {
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timer->val = 0;
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timer->st = 0;
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if (timer->it_ena)
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qemu_irq_raise(timer->irq);
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}
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} else
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qemu_del_timer(timer->timer);
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}
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@ -3502,12 +3529,11 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
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{
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int iomemtype;
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s->pwl.base = base;
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omap_pwl_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
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omap_pwl_writefn, s);
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cpu_register_physical_memory(s->pwl.base, 0x800, iomemtype);
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cpu_register_physical_memory(base, 0x800, iomemtype);
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omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
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}
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@ -3597,13 +3623,12 @@ static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
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{
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int iomemtype;
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s->pwt.base = base;
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s->pwt.clk = clk;
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omap_pwt_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
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omap_pwt_writefn, s);
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cpu_register_physical_memory(s->pwt.base, 0x800, iomemtype);
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cpu_register_physical_memory(base, 0x800, iomemtype);
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}
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/* Real-time Clock module */
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@ -4207,6 +4232,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
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* USB Host fffba000 - fffba7ff
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* FAC fffba800 - fffbafff
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* HDQ/1-Wire fffbc000 - fffbc7ff
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* TIPB switches fffbc800 - fffbcfff
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* LED1 fffbd000 - fffbd7ff
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* LED2 fffbd800 - fffbdfff
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* Mailbox fffcf000 - fffcf7ff
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15
hw/omap.h
15
hw/omap.h
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@ -646,14 +646,23 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
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# define OMAP_RO_REG(paddr) \
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printf("%s: Read-only register " OMAP_FMT_plx "\n", \
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__FUNCTION__, paddr)
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# define OMAP_8B_REG(paddr) \
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# define TCMI_VERBOSE 1
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# ifdef TCMI_VERBOSE
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# define OMAP_8B_REG(paddr) \
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printf("%s: 8-bit register " OMAP_FMT_plx "\n", \
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__FUNCTION__, paddr)
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# define OMAP_16B_REG(paddr) \
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# define OMAP_16B_REG(paddr) \
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printf("%s: 16-bit register " OMAP_FMT_plx "\n", \
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__FUNCTION__, paddr)
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# define OMAP_32B_REG(paddr) \
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# define OMAP_32B_REG(paddr) \
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printf("%s: 32-bit register " OMAP_FMT_plx "\n", \
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__FUNCTION__, paddr)
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# else
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# define OMAP_8B_REG(paddr)
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# define OMAP_16B_REG(paddr)
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# define OMAP_32B_REG(paddr)
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# endif
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#endif /* hw_omap_h */
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@ -742,4 +742,8 @@ void omap_clk_init(struct omap_mpu_state_s *mpu)
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j->multiplier = j->multiplier ?: 1;
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j ++;
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}
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for (j = mpu->clks; count --; j ++) {
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omap_clk_update(j);
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omap_clk_rate_update(j);
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}
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}
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