target/arm: Implement SVE2 floating-point pairwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Stephen Long
Peter Maydell
parent
5ff2838d3d
commit
b87dbeebe6
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@ -2443,3 +2443,38 @@ DEF_HELPER_FLAGS_3(sve2_uqxtnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve2_sqxtunt_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve2_sqxtunt_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve2_sqxtunt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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@ -1284,3 +1284,11 @@ UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl
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UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl
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SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl
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SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl
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## SVE2 floating-point pairwise operations
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FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm
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FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm
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FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm
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FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm
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FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm
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@ -895,6 +895,52 @@ DO_ZPZZ_PAIR_D(sve2_sminp_zpzz_d, int64_t, DO_MIN)
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#undef DO_ZPZZ_PAIR
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#undef DO_ZPZZ_PAIR_D
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#define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \
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void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
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void *status, uint32_t desc) \
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{ \
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intptr_t i, opr_sz = simd_oprsz(desc); \
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for (i = 0; i < opr_sz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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TYPE n0 = *(TYPE *)(vn + H(i)); \
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TYPE m0 = *(TYPE *)(vm + H(i)); \
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TYPE n1 = *(TYPE *)(vn + H(i + sizeof(TYPE))); \
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TYPE m1 = *(TYPE *)(vm + H(i + sizeof(TYPE))); \
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if (pg & 1) { \
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*(TYPE *)(vd + H(i)) = OP(n0, n1, status); \
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} \
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i += sizeof(TYPE), pg >>= sizeof(TYPE); \
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if (pg & 1) { \
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*(TYPE *)(vd + H(i)) = OP(m0, m1, status); \
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} \
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i += sizeof(TYPE), pg >>= sizeof(TYPE); \
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} while (i & 15); \
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} \
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}
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DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_h, float16, H1_2, float16_add)
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DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_s, float32, H1_4, float32_add)
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DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_d, float64, , float64_add)
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DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_h, float16, H1_2, float16_maxnum)
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DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_s, float32, H1_4, float32_maxnum)
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DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_d, float64, , float64_maxnum)
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DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_h, float16, H1_2, float16_minnum)
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DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_s, float32, H1_4, float32_minnum)
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DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_d, float64, , float64_minnum)
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DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_h, float16, H1_2, float16_max)
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DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_s, float32, H1_4, float32_max)
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DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_d, float64, , float64_max)
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DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_h, float16, H1_2, float16_min)
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DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_s, float32, H1_4, float32_min)
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DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_d, float64, , float64_min)
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#undef DO_ZPZZ_PAIR_FP
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/* Three-operand expander, controlled by a predicate, in which the
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* third operand is "wide". That is, for D = N op M, the same 64-bit
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* value of M is used with all of the narrower values of N.
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@ -6697,3 +6697,28 @@ static bool trans_SQXTUNT(DisasContext *s, arg_rri_esz *a)
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};
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return do_sve2_narrow_extract(s, a, ops);
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}
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static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
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gen_helper_gvec_4_ptr *fn)
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{
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if (!dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_zpzz_fp(s, a, fn);
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}
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#define DO_SVE2_ZPZZ_FP(NAME, name) \
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static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
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{ \
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static gen_helper_gvec_4_ptr * const fns[4] = { \
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NULL, gen_helper_sve2_##name##_zpzz_h, \
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gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d \
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}; \
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return do_sve2_zpzz_fp(s, a, fns[a->esz]); \
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}
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DO_SVE2_ZPZZ_FP(FADDP, faddp)
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DO_SVE2_ZPZZ_FP(FMAXNMP, fmaxnmp)
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DO_SVE2_ZPZZ_FP(FMINNMP, fminnmp)
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DO_SVE2_ZPZZ_FP(FMAXP, fmaxp)
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DO_SVE2_ZPZZ_FP(FMINP, fminp)
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