target/sparc: Move EDGE* to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
da68140604
commit
b88ce6f246
@ -35,6 +35,9 @@ CALL 01 i:s30
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@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
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@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
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&r_r_r rd rs1 rs2
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@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
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{
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[
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STBAR 10 00000 101000 01111 0 0000000000000
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@ -231,7 +234,24 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri
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DONE 10 00000 111110 00000 0 0000000000000
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RETRY 10 00001 111110 00000 0 0000000000000
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NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
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{
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[
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EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
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EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r
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EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r
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EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r
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EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r
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EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r
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EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r
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EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r
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EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r
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EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r
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EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r
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EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r
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]
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NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
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}
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NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
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##
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@ -2728,93 +2728,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
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}
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}
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static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
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int width, bool cc, bool left)
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{
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TCGv lo1, lo2;
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uint64_t amask, tabl, tabr;
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int shift, imask, omask;
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if (cc) {
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tcg_gen_mov_tl(cpu_cc_src, s1);
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tcg_gen_mov_tl(cpu_cc_src2, s2);
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tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
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dc->cc_op = CC_OP_SUB;
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}
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/* Theory of operation: there are two tables, left and right (not to
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be confused with the left and right versions of the opcode). These
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are indexed by the low 3 bits of the inputs. To make things "easy",
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these tables are loaded into two constants, TABL and TABR below.
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The operation index = (input & imask) << shift calculates the index
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into the constant, while val = (table >> index) & omask calculates
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the value we're looking for. */
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switch (width) {
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case 8:
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imask = 0x7;
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shift = 3;
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omask = 0xff;
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if (left) {
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tabl = 0x80c0e0f0f8fcfeffULL;
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tabr = 0xff7f3f1f0f070301ULL;
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} else {
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tabl = 0x0103070f1f3f7fffULL;
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tabr = 0xfffefcf8f0e0c080ULL;
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}
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break;
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case 16:
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imask = 0x6;
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shift = 1;
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omask = 0xf;
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if (left) {
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tabl = 0x8cef;
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tabr = 0xf731;
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} else {
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tabl = 0x137f;
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tabr = 0xfec8;
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}
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break;
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case 32:
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imask = 0x4;
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shift = 0;
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omask = 0x3;
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if (left) {
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tabl = (2 << 2) | 3;
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tabr = (3 << 2) | 1;
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} else {
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tabl = (1 << 2) | 3;
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tabr = (3 << 2) | 2;
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}
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break;
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default:
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abort();
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}
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lo1 = tcg_temp_new();
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lo2 = tcg_temp_new();
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tcg_gen_andi_tl(lo1, s1, imask);
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tcg_gen_andi_tl(lo2, s2, imask);
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tcg_gen_shli_tl(lo1, lo1, shift);
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tcg_gen_shli_tl(lo2, lo2, shift);
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tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
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tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
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tcg_gen_andi_tl(lo1, lo1, omask);
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tcg_gen_andi_tl(lo2, lo2, omask);
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amask = -8;
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if (AM_CHECK(dc)) {
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amask &= 0xffffffffULL;
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}
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tcg_gen_andi_tl(s1, s1, amask);
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tcg_gen_andi_tl(s2, s2, amask);
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/* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
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tcg_gen_and_tl(lo2, lo2, lo1);
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tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);
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}
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static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
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{
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TCGv tmp = tcg_temp_new();
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@ -2877,6 +2790,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
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# define avail_64(C) true
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# define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
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# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
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# define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1)
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# define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2)
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#else
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# define avail_32(C) true
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# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
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@ -2887,6 +2802,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
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# define avail_64(C) false
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# define avail_GL(C) false
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# define avail_HYPV(C) false
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# define avail_VIS1(C) false
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# define avail_VIS2(C) false
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#endif
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/* Default case for non jump instructions. */
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@ -4187,6 +4104,113 @@ static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
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return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc);
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}
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static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
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int width, bool cc, bool left)
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{
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TCGv dst, s1, s2, lo1, lo2;
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uint64_t amask, tabl, tabr;
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int shift, imask, omask;
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dst = gen_dest_gpr(dc, a->rd);
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s1 = gen_load_gpr(dc, a->rs1);
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s2 = gen_load_gpr(dc, a->rs2);
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if (cc) {
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tcg_gen_mov_tl(cpu_cc_src, s1);
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tcg_gen_mov_tl(cpu_cc_src2, s2);
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tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
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dc->cc_op = CC_OP_SUB;
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}
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/*
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* Theory of operation: there are two tables, left and right (not to
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* be confused with the left and right versions of the opcode). These
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* are indexed by the low 3 bits of the inputs. To make things "easy",
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* these tables are loaded into two constants, TABL and TABR below.
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* The operation index = (input & imask) << shift calculates the index
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* into the constant, while val = (table >> index) & omask calculates
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* the value we're looking for.
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*/
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switch (width) {
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case 8:
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imask = 0x7;
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shift = 3;
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omask = 0xff;
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if (left) {
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tabl = 0x80c0e0f0f8fcfeffULL;
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tabr = 0xff7f3f1f0f070301ULL;
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} else {
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tabl = 0x0103070f1f3f7fffULL;
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tabr = 0xfffefcf8f0e0c080ULL;
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}
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break;
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case 16:
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imask = 0x6;
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shift = 1;
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omask = 0xf;
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if (left) {
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tabl = 0x8cef;
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tabr = 0xf731;
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} else {
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tabl = 0x137f;
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tabr = 0xfec8;
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}
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break;
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case 32:
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imask = 0x4;
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shift = 0;
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omask = 0x3;
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if (left) {
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tabl = (2 << 2) | 3;
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tabr = (3 << 2) | 1;
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} else {
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tabl = (1 << 2) | 3;
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tabr = (3 << 2) | 2;
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}
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break;
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default:
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abort();
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}
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lo1 = tcg_temp_new();
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lo2 = tcg_temp_new();
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tcg_gen_andi_tl(lo1, s1, imask);
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tcg_gen_andi_tl(lo2, s2, imask);
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tcg_gen_shli_tl(lo1, lo1, shift);
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tcg_gen_shli_tl(lo2, lo2, shift);
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tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
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tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
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tcg_gen_andi_tl(lo1, lo1, omask);
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tcg_gen_andi_tl(lo2, lo2, omask);
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amask = address_mask_i(dc, -8);
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tcg_gen_andi_tl(s1, s1, amask);
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tcg_gen_andi_tl(s2, s2, amask);
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/* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
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tcg_gen_and_tl(lo2, lo2, lo1);
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tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);
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gen_store_gpr(dc, a->rd, dst);
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return advance_pc(dc);
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}
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TRANS(EDGE8cc, VIS1, gen_edge, a, 8, 1, 0)
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TRANS(EDGE8Lcc, VIS1, gen_edge, a, 8, 1, 1)
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TRANS(EDGE16cc, VIS1, gen_edge, a, 16, 1, 0)
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TRANS(EDGE16Lcc, VIS1, gen_edge, a, 16, 1, 1)
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TRANS(EDGE32cc, VIS1, gen_edge, a, 32, 1, 0)
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TRANS(EDGE32Lcc, VIS1, gen_edge, a, 32, 1, 1)
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TRANS(EDGE8N, VIS2, gen_edge, a, 8, 0, 0)
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TRANS(EDGE8LN, VIS2, gen_edge, a, 8, 0, 1)
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TRANS(EDGE16N, VIS2, gen_edge, a, 16, 0, 0)
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TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1)
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TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0)
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TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1)
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static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
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{
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TCGv dst, src1, src2;
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@ -5075,89 +5099,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
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switch (opf) {
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case 0x000: /* VIS I edge8cc */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x001: /* VIS II edge8n */
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x002: /* VIS I edge8lcc */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x003: /* VIS II edge8ln */
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x004: /* VIS I edge16cc */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x005: /* VIS II edge16n */
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x006: /* VIS I edge16lcc */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x007: /* VIS II edge16ln */
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x008: /* VIS I edge32cc */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x009: /* VIS II edge32n */
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x00a: /* VIS I edge32lcc */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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case 0x00b: /* VIS II edge32ln */
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CHECK_FPU_FEATURE(dc, VIS2);
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cpu_src1 = gen_load_gpr(dc, rs1);
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cpu_src2 = gen_load_gpr(dc, rs2);
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gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
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gen_store_gpr(dc, rd, cpu_dst);
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break;
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g_assert_not_reached(); /* in decodetree */
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case 0x010: /* VIS I array8 */
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CHECK_FPU_FEATURE(dc, VIS1);
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cpu_src1 = gen_load_gpr(dc, rs1);
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